ZHCSLO2E October 2020 – January 2021 DAC5652
PRODUCTION DATA
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | 38 | I | Analog ground |
AVDD | 47 | I | Analog supply voltage |
BIASJ_A | 44 | O | Full-scale output current bias for DACA |
BIASJ_B | 41 | O | Full-scale output current bias for DACB |
CLKA/CLKIQ | 18 | I | Clock input for DACA, CLKIQ in interleaved mode |
CLKB/RESETIQ | 19 | I | Clock input for DACB, RESETIQ in interleaved mode |
DA[9:0] | 1-10 | I | Data port A. DA9 is MSB and DA0 is LSB. Internal pulldown. |
DB[9:0] | 23-32 | I | Data port B. DB9 is MSB and DB0 is LSB. Internal pulldown. |
DGND | 15, 21 | I | Digital ground |
DVDD | 16, 22 | I | Digital supply voltage |
EXTIO | 43 | I/O | Internal reference output (bypass with 0.1 μF to AGND) or external reference input |
GSET | 42 | I | Gain-setting mode: H – 1 resistor, L – 2 resistors. Internal pullup. |
IOUTA1 | 46 | O | DACA current output. Full-scale with all bits of DA high. |
IOUTA2 | 45 | O | DACA complementary current output. Full-scale with all bits of DA low. |
IOUTB1 | 39 | O | DACB current output. Full-scale with all bits of DB high. |
IOUTB2 | 40 | O | DACB complementary current output. Full-scale with all bits of DB low. |
MODE | 48 | I | Mode Select: H – Dual Bus, L – Interleaved. Internal pullup. |
NC | 11-14, 33-36 | - | Factory use only. Pins must be connected to DGND or left unconnected. |
SLEEP | 37 | I | Sleep function control input: H – DAC in power-down mode, L – DAC in operating mode. Internal pulldown. |
WRTA/WRTIQ | 17 | I | Input write signal for PORT A (WRTIQ in interleaving mode) |
WRTB/SELECTIQ | 20 | I | Input write signal for PORT B (SELECTIQ in interleaving mode) |