SBAS334D November   2004  – July 2016 DAC5675A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description Continued
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics
    6. 7.6 AC Electrical Characteristics
    7. 7.7 Digital Specifications
    8. 7.8 Operational Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital Inputs
      2. 8.3.2 Clock Input
      3. 8.3.3 Supply Inputs
      4. 8.3.4 DAC Transfer Function
      5. 8.3.5 Reference Operation
      6. 8.3.6 Analog Current Outputs
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
    6. 12.6 Device Nomenclature
      1. 12.6.1 Definitions of Specifications and Terminology
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Pin Configuration and Functions

PHP Package
48-Pin (HTQFP)
Top View
Note: Thermal pad size: 4.5 mm x 4.5 mm (min), 5.5 mm x 5.5 mm (max)

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AGND 19, 41, 46, 47 I Analog negative supply voltage (ground); pin 47 internally connected to PowerPAD.
AVDD 20, 42, 45, 48 I Analog positive supply voltage.
BIASJ 39 O Full-scale output current bias.
CLK 22 I External clock input.
CLKC 21 I Complementary external clock input.
D(13:0)A 1, 3, 5, 7, 9, 11, 13, 23, 25, 27, 29, 31, 33, 35 I LVDS positive input, data bits 0 through 13.
D13A is most significant data bit (MSB).
D0A is least significant data bit (MSB).
D(13:0)B 2, 4, 6, 8, 10, 12, 14, 24, 26, 28, 30, 32, 34, 36 I LVDS negative input, data bits 0 through 13.
D13B is most significant data bit (MSB).
D0B is least significant data bit (MSB).
DGND 16, 18 I Digital negative supply voltage (ground).
NC 38 -— Not connected in chip. Can be high or low.
DVDD 15, 17 I Digital positive supply voltage.
EXTIO 40 I/O Internal reference output or external reference input. Requires a 0.1µF decoupling capacitor to AGND when used as reference output.
IOUT1 43 O DAC current output. Full-scale when all input bits are set to '0'. Connect reference side of DAC load resistors to AVDD.
IOUT2 44 O DAC complementary current output. Full-scale when all input bits are set to '1'. Connect reference side of DAC load resistors to AVDD.
SLEEP 37 I Asynchronous hardware power down input. Active high. Internal pulldown.
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