ZHCSEG7A December 2015 – January 2016 DAC60096
PRODUCTION DATA.
It is highly recommended that AVCC is supplied prior to AVSS. DVDD sequencing is not critical. The recommended sequence is AVCC followed by AVSS with DVDD and the REF[1,2] inputs applied last.
| MIN | TYP | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| Supply voltage | AVCC | 11.2 | 12 | 12.6 | V | |
| AVSS | –12.6 | –12 | –11.2 | V | ||
| DVDD | 3 | 3.3 | 5.5 | V | ||
| AVCC to AVSS | 22.4 | 24 | 25.2 | V | ||
| EXTERNAL REFERENCE INPUTS | ||||||
| VREF | Reference input voltage | REF1 and REF2 input pins | 2.475 | 2.5 | 2.525 | V |
The DAC60096 includes a power-on reset function. After the DVDD supply has been established a POR event is issued. The POR causes all registers to initialize to their default values and communication with the device is valid only after a 250 µs power-on-reset delay. The default value for all DACs is zero-code.
A power failure on DVDD also results in a power-on-reset event. The PWRM register (address 0x8) can be used to monitor a DVDD power failure. After power-up the PWRM register is set to 0xCAFE. Any register write to the PWRM register changes its contents to 0xABBA. If a PWRM register read returns 0xCAFE either the PWRM register has not been initialized or a DVDD power failure has occured.
The device also includes an AVCC power failure detection circuit. In contrast to a DVDD power failure, a collapse in AVCC does not result in a reset event. An AVCC power failure forces all DACs to go into clear state but does not reset the DAC data register values which enables the device to return to normal operation once AVCC recovers. Even though the DACs are loaded with zero-code during an AVCC power failure, it is important to note that this does not necessarily indicate the DAC outputs will be at 0 V due to AVCC being outside of its supply voltage range.
As long as DVDD and AVCC remain above their specified high threshold a power failure event will not occur. In order to ensure a DVDD or AVCC collapse is registered as such by the device, these supplies must be below their corresponding low threshold for at least 1 ms. When the supplies drop below their high threshold but remain over the lower one (shown as the undefined region of Figure 54 and Figure 55), the device may or may not reset (DVDD) or go into clear state (AVCC) under all specified temperature and power-supply conditions.
A device hardware reset event is initiated by a minimum 500 ns logic low on the RESET pin. A hardware reset causes all registers to initialize to their default values and communication with the device is valid only after a 50 µs reset delay. The default value for all DACs is zero-code.
A subsystem software reset event is initiated by writing 0xA5A5 to the SWR register (address 0x7) for that particular subsystem. The software reset command is triggered on the CS rising edge of the instruction. As with the hardware reset, a software reset causes all registers to initialize to their default values and communication with the device is valid only after a 50 µs. Note, however, that the reset only applies to the subsystem being addressed during the command. In order to reset the entire device as a hardware reset does, a software reset command should be issued to each of the four subsystems in the device.