10.1 Layout Guidelines

• Bypass all power-supply pins to ground with a low ESR ceramic bypass capacitor. The typical recommended bypass capacitance is 0.1-µF to 0.22-µF ceramic with a X7R or NP0 dielectric.
• Place power supplies and VREFH/L bypass capacitors close to pins to minimize inductance and optimize performance. Inner supply and reference pads can connect to the bypass arrangement on the bottom layer of the PCB through vias to minimize trace length. This is illustrated in Figure 56 and Figure 59.
• Include a 100-nF bypass capacitor for both internal reference inputs between this pin and their respective ground pins.
• Use a high-quality ceramic type NP0 or X7R for optimal performance across temperature, and low dissipation factor.
• Make sure that the digital and analog sections have proper placement with respect to the digital pins and analog pins of the DAC60096 device. The separation of analog and digital blocks allow for better design and practice because it reduces coupling into neighboring blocks, and minimizes the interaction between analog and digital return currents.

10.2 Layout Examples

10.2.2 Standard Layout Example

Only through-hole vias are included in this layout. Bypass capacitors are placed as close to their respective device pads. Bottom bypass brought out from device. This layout can lead to increased trace length, which will increase the series inductance of the net making it more susceptible to noise and voltage spikes. Figure 60 to Figure 61 show the board layouts.

Figure 60. DAC60096 Example Board Layout – Top Layer

Figure 61. DAC60096 Example Board Layout – Bottom Layer