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ZHCSEG7A December 2015 – January 2016 DAC60096

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7 Detailed Description

7.1 Overview

The DAC60096 is a low-power, 96-channel, 12-bit, digital-to-analog converter (DAC). The device provides
±10.5-V unbuffered bipolar voltage outputs while maintaining extremely low-power operation and good linearity. The device integrates dedicated reference buffers that enable operation from an external 2.5-V reference source.

The DAC60096 can be set up to clear or update all DACs simultaneously. In addition a versatile external conversion trigger allows each DAC to operate as an amplitude-independent square-wave generator. The device incorporates a reset circuit that ensures all DAC outputs power up and remain at zero scale prior to device configuration.

The DAC60096 features simplify the design of systems requiring a high number of precise analog control signals such as those found in optical communications switches and attenuators.

The DAC60096 is designed as four DAC subsystems. Each DAC subsystem is configured independently through a high speed 4-wire serial interface compatible with industry standard microprocessors and microcontrollers. The DAC60096 is characterized for operation over the temperature range of –40°C to +85°C, and is available in a 196-ball, 15-mm × 15-mm, 1-mm pitch BGA package.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Digital-to-Analog Converters (DACs)

The DAC60096 is a 96-channel, 12-bit digital-to-analog converter (DAC) with integrated reference buffers. Each DAC output consists of an R-2R ladder configuration as shown in Figure 32.

The DAC60096 includes reference buffers that enable bipolar DAC output voltages of ±10.5 V from a 2.5-V reference source. The outputs of the reference buffers drive the R-2R ladders.

Figure 32. R-2R Ladder Configuration

7.3.1.1 DAC Transfer Function

The DAC60096 integrates dedicated reference buffers that enable operation from an external 2.5-V reference source. The reference buffers generate the voltages, VREFH and VREFL, required to drive the DAC R-2R ladders.

Equation 1. DAC60096 equa1_slaseb3.gif

Equation 2. DAC60096 equa2_slaseb3.gif

where V_REF is the reference input voltage at pins REF1 and REF2.

Input data are written to the individual DAC data registers in 12-bit twos complement format. After power-on or a reset event, all DAC registers are set to zero scale. The DAC transfer function is given by Equation 3.

Equation 3. DAC60096 equa3_slaseb3.gif

where Code is the signed decimal equivalent of the binary code loaded to the DAC register and ranges from
-2048 to 2047 (See Table 1).

Table 1. DAC Data Format

DIGITAL CODE	SIGNED DECIMAL VALUE	DAC OUTPUT VOLTAGE (V)
0111 1111 1111	+2047	10.49487
0111 1111 1110	+2046	10.48975
0000 0000 0001	+1	0.005127
0000 0000 0000	0	0
1111 1111 1111	–1	–0.005127
1000 0000 0001	–2047	–10.49487
1000 0000 0000	–2048	–10.5

7.3.1.2 DAC Register Structure

Each DAC in the device incorporates two data registers: Register A and Register B. These two data registers and the TRIGG pin enable toggle mode operation. Alternatively, if the TRIGG pin is left fixed the device is in DC mode operation and only one of the data registers is used to control the DAC output (Register A by default).

Data written to the DAC data registers is initially stored in the DAC buffer registers. Transfer of data from the DAC buffer registers to the active DAC registers can be set to happen immediately (asynchronous mode) or initiated by an LDAC trigger (synchronous mode). After data are transferred to the DAC active registers, the DAC outputs are updated. When the host reads from a DAC data register, the value held in the DAC buffer register is returned (not the value held in the DAC active register).

The DAC update mode is determined by the status of the LDAC input pin. If the LDAC pin is held low the device is in asynchronous mode. In asynchronous mode, a write to a DAC data register results in an immediate update of the DAC active register and the corresponding output. If LDAC is held high, the device is in synchronous mode. In synchronous mode, writing to a DAC data register does not automatically update the DAC output. Instead, the update occurs only after an LDAC trigger occurs. An LDAC trigger is generated either through a high-to-low transition on the LDAC pin in which case all 96 DACs update at the same time or by the self-clearing LDAC bit in each of the four subsystems CON registers (address 0x4, bit 15) which enables synchronization of all the DACs in the selected subsystem.

After the DAC outputs have been configured, a clear event enables the DACs to be loaded with zero-code while retaining the previously programmed values, thus allowing the possibility to return to the voltage being output before the clear event was issued. Note that the DAC data registers can be updated while the device is in clear state allowing the DACs to output new values upon return to normal operation. When the device exits the clear state the DAC outputs are immediately loaded with the data in the DAC active registers.

The device is set into clear state through the CLEAR pin. Setting the CLEAR pin low forces all 96 DACs into clear state. Setting the CLEAR pin back high returns all DACs to normal operation. Alternatively, the CLRDAC bits in each of the four subsystems CON registers (Address 0x4, bits [5:4]) can be used to enter or exit clear state at a subsystem level.

Figure 33. DAC60096 DAC Block Diagram

7.3.2 Reference Specifications

The DAC60096 integrates dedicated reference buffers that enable operation from an external 2.5-V reference source. The reference buffers generate the ±10.5-V levels used to drive the DACs in the device. A 100-nF bypass capacitor should be placed between the REF[1,2] input pins and REFGND[1,2]. Additionally a compensation 100-nF bypass capacitor for each VREFH_n and VREFL_n pin (n = G1, G2, G3, G4, G5, G6, G7 or G8) is required and should be placed as close as possible to the pins.

Figure 34. Reference Operation

7.4 Device Functional Modes

7.4.1 Toggle Mode

Each DAC in the device incorporates two DAC registers: Register A and Register B. The TRIGG pin is used to switch the DAC outputs back and forth between the contents of the two DAC specific registers. The DAC registers are prepared for trigger mode operation on a TRIGG rising edge and the outputs are toggled on each following high-to-low transition. This feature enables the generation of 96 amplitude independent square-waves.

The device incorporates an auto-populate feature that simplifies register configuration in toggle mode. Auto-populate is enabled by the APB bits in the CON register (address 0x4, bits [1:0]). When auto-populate is enabled, a Register A update automatically loads Register B with the negative value of the data written to A. Although the Register B data can be modified by a direct register write, this update does not auto-populate the Register A contents.

The STATS output pin is used to identify the active register. A logic-low is output for Register A and logic-high for register B. The STATS pin is in high impedance mode by default and must be enabled by the SDRV bits in the CON register for subsystem 1 (address 0x4, bits [9:8]). The SDRV bits in the other three subsystems should be set to high impedance mode (default mode).The toggling rate of the STATS terminal is determined by the SDIV register (address 0x9). The SDIV register should only be updated after a device reset and before configuring the DAC outputs The STATS output pin toggles on every 2^SDIV trigger pulse (SDIV = 0, 1, …, 6).

7.4.2 DC Mode

A fixed TRIGG pin puts the device in DC mode operation. In DC mode only one of the two DAC data registers is used to control the DAC output. If no TRIGG rising edge is detected by the device after power-up, Register A is by default the active register.

7.5 Programming

The DAC60096 is controlled through a flexible four-wire serial interface that is compatible with SPI type interfaces used on many microcontrollers and DSP controllers. The interface provides read/write access to all registers of the DAC60096.

For simplification of the register structure, communication to the device is done at a subsystem level through the PTR global pointer register (address 0x6). Subsystem addressing is done through SID[1:0], where subsystem 1 is the default setting. Access to all other registers in the device will affect only the subsystem selected by SID. The DAC pointer setting, DPTR[4:0], also in the PTR register allows access to the data registers (BUFA and BUFB) for any of the DACs in the chosen subsystem.

Each serial interface access cycle is exactly 24 bits long. A frame is initiated by asserting the CS pin low. The frame ends when the CS pin is deasserted high. The frame's first byte input to SDI is the instruction cycle which identifies the request as a read or write, streaming or single, and the 4-bit address to be accessed. The following bits in the frame form the data cycle. For all writes, data are clocked on the rising edge of SCLK. On read access, data are clocked out on the SDO pin on either the falling edge or rising edge of SCLK according to the PHAINV setting in each of the four subsystems CON registers (address 0x4, bits [7:6]).

Table 2. Serial Interface Cycle

Bit	Field	Description
23	R/W	Identifies the communication as a read or write command to the addressed register. R/W = 0 sets a write operation. R/W = 1 sets a read operation.
22	S	Identifies the communication as a streaming operation. S = 0 is used for single command instructions. Bit = 1 is used for streaming operation.
21:18	A[3:0]	Register address. Specifies the register to be accessed during the read or write operation.
17:16	Reserved	Reserved. Set to zeros for proper operation.
15:0	D[15:0]	Data cycle bits. If a write command, the data cycle bits are the values to be written to the register with address A[3:0] If a read command, the data cycle bits are don't care values.

Figure 35. Serial Interface Write Bus Cycle

Figure 36. Serial Interface Read Bus Cycle

In order to simplify write or read operations to multiple DACs in a subsystem, streaming mode is supported. In streaming mode, multiple bytes of data can be written to or read from the DAC60096 without specifically providing instructions for each byte and is implemented by continually holding the CS pin active and continuing to shift new data in or old data out of the device.

The DAC60096 starts reading or writing data to the DAC data register selected by the PTR register and automatically increments the DAC pointer (DPTR) as long as the CS pin is asserted. If the last DAC in the chosen subsystem has been reached and the CS pin is still asserted, the data register for this DAC will be overwritten with the new data.

Figure 37. Serial Interface Streaming Write Cycle

Figure 38. Serial Interface Streaming Read Cycle

7.5.1 Frame Error Checking

If the DAC60096 is used in a noisy environment, error checking can be used to check the integrity of the serial interface data communication between the device and the host processor. The frame error checking scheme is based on the CRC-CCITT-16 polynomial x¹⁶ + x¹² + x⁵ + 1 (that is, 0x1021). The CRC register (address 0x5) stores the CRC computation for each single-command or streaming serial interface data write. Reading the CRC register resets its contents to 0xFFFF.

Only valid data cycles are included in the CRC computation. For single-command instructions CRC is calculated and updated only after 16 data bits are received. If a data cycle is longer than 16 bits, the additional bits are not included into the CRC calculation. For streaming commands CRC is calculated and updated on the multiple 16-bit data cycles received. If the number of data bits received is not a multiple of 16, the modulo 16 bits are discarded from the CRC calculation.

7.6 Register Maps

Communication to the DAC60096 is done at a subsystem level. Subsystem addressing is done through the global pointer register, SID[1:0]. Each subsystem has 16 registers. Access to the data registers of any of the DACs in the chosen subsystem is done through a DAC pointer, DPTR[4:0].

Figure 39. Register Configuration

Table 3. Register Map

REGISTER	TYPE	RESET	ADDRESS				REGISTER SETUP
REGISTER	TYPE	RESET	A3	A2	A1	A0	D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
BUFA	R/W	0000	0	0	0	0	BUFA												0	0	0	0
BUFB	R/W	0000	0	0	0	1	BUFB												0	0	0	0
RESERVED	--	0000	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
RESERVED	--	0000	0	0	1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
CON	R/W	0555	0	1	0	0	LDAC	0	0	0	SDO2x		SDRV		PHAINV		CLRDAC		0	1	APB
CRC	R	FFFF	0	1	0	1	CRC
PTR	R	0000	0	1	1	0	0	0	SID		0	0	0	0	0	0	0	DPTR
SWR	R/W	0000	0	1	1	1	SWR
PWRM	R/W	CAFE	1	0	0	0	PWRM
SDIV	R/W	0000	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	SDIV
RESERVED	--	0000	0xA – 0xF				------

7.6.1 8.5.1 BUFA Register (address = 0x0) [reset = 0x0000]

Figure 40. BUFA Register

15	14	13	12	11	10	9	8
BUFA
R/W

7	6	5	4	3	2	1	0
BUFA				RESERVED
R/W				R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4. BUFA Register

Bit	Field	Type	Reset	Description
15:4	BUFA	R/W	0000	Double-buffer MSB aligned 12-bit data for DAC register A. The specific DAC accessed by this register must be first set by the subsystem address (SID) and DAC pointer (DPTR).
3:0	Reserved	R/W	0000	Not used

7.6.2 BUFB Register (address = 0x1) [reset = 0x0000]

Figure 41. BUFB Register

15	14	13	12	11	10	9	8
BUFB
R/W

7	6	5	4	3	2	1	0
BUFB				Reserved
R/W				R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 5. BUFB Register

Bit	Field	Type	Reset	Description
15:4	BUFB	R/W	0000	Double-buffer MSB aligned 12-bit data for DAC register B. The specific DAC accessed by this register must be first set by the subsystem address (SID) and DAC pointer (DPTR).
3:0	Reserved	R/W	0000	Not used

7.6.3 CON Register (address = 0x4) [reset = 0x0555]

Figure 42. CON Register

15	14	13	12	11	10	9	8
LDAC	Reserved			SDO2x[1:0]		SDRV[1:0]
R/W	R/W			R/W		R/W

7	6	5	4	3	2	1	0
PHAINV[1:0]		CLRDAC[1:0]		Reserved		APB[1:0]
R/W		R/W		R/W		R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6. CON Register

Bit	Field	Type	Reset	Description
15	LDAC	R/W	0	Setting this bit to 1 issues an LDAC trigger at CS rising edge. Self-clearing bit.
14:12	Reserved	R/W	000	Not used.
11:10	SDO2x[1:0]	R/W	01	SDO 1x/2x drive strength: 01: 1x (default) 10: 2x Writing 00 or 11 has no effect
9:8	SDRV[1:0]	R/W	01	SDRV control STATS pin drive type: 01: Hi-Z. STATS pin is disabled (default) 10: CMOS Push-pull output. Should only be enabled for subsystem 1. Writing 00 or 11 has no effect
7:6	PHAINV[1:0]	R/W	01	PHAINV controls SDO output edge: 01: SCLK NegEdge (default) 10: SCLK PosEdge Writing 00 or 11 has no effect
5:4	CLRDAC[1:0]	R/W	01	Clear DAC state control: 01: Normal operating state (default) 10: Clear DAC state Writing 00 or 11 has no effect
3:2	Reserved	R/W	01	Reserved for factory use
1:0	APB[1:0]	R/W	01	Auto populate B: 01: Auto-populates BUFB with the negative value of BUFA after each BUFA register write. Writing to BUFB has no auto-populate effect (default) 10: Disable auto populate B feature Writing 00 or 11 has no effect

7.6.4 CRC Register (address = 0x5) [reset = 0xFFF]

Figure 43. CRC Register

15	14	13	12	11	10	9	8
CRC[15:0]
R

7	6	5	4	3	2	1	0
CRC[15:0]
R

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. CRC Register

Bit	Field	Type	Reset	Description
15:0	CRC[15:0]	R	FFFF	Stores the CRC computation data for each SPI data write. CRC includes stream writes. The address byte is not included in the CRC computation. Reading Reg CRC resets current CRC value to 0xFFFF. CRC is calculated when CS is enabled and the data cycle contains a multiple of 16 bits. The redundant data are not written into the register. CRC-CCITT polynomial is used x¹⁶ + x¹² + x⁵+ 1, or in hex: 0x1021 with default 0xFFFF.

Figure 44. CRC CCITT 16

7.6.5 PTR Register (address = 0x6) [reset = 0x0000]

Figure 45. PTR Register

15	14	13	12	11	10	9	8
Reserved		SID[1:0]		Reserved
R/W		R/W		R/W

7	6	5	4	3	2	1	0
Reserved			DPTR[4:0]
R/W			R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. PTR Register

Bit	Field	Type	Reset	Description
15:14	Reserved	R/W	00	Reserved for factory use
13:12	SID[1:0]	R/W	00	Subsystem address: 00: Subsystem 1 01: Subsystem 2 10: Subsystem 3 11: Subsystem 4
11:8	Reserved	R/W	0000	Not used
7:5	Reserved	R/W	000	Reserved for factory use
4:0	DPTR[4:0]	R/W	0000	DAC pointer

7.6.6 SWR Register (address = 0x7) [reset = 0x0000]

Figure 46. SWR Register

15	14	13	12	11	10	9	8
SWR
R/W

7	6	5	4	3	2	1	0
SWR
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. SWR Register

Bit	Field	Type	Reset	Description
15:0	SWR	R/W	0000	Writing 0xA5A5 to this register generates a software reset on the CS rising edge of the command for a subsystem. The software reset is similar to a hardware reset, which resets all registers and logic states. Reading this register gives the hardware version of the subsystem.

7.6.7 PWRM Register (address = 0x6) [reset = 0xCAFE]

Figure 47. PWRM Register

15	14	13	12	11	10	9	8
PWRM
R/W

7	6	5	4	3	2	1	0
PWRM
R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. PWRM Register

Bit	Field	Type	Reset	Description
15:0	PWRM	R/W	0000	DV_DDPower Monitor: After device power up, the PWRM register is 0xCAFE. Any register write to PWRM sets PWRM to 0xABBA. PWRM is reset to 0xCAFE after a DVDD collapse initiated POR event. Reading PWRM with value 0xCAFE indicates power failure or uninitialized value. The system controller can monitor PWRM to check for active power status. The device toggles the PWRM value after every PWRM register read. If the current read value is 0xABBA, the next read value will be 0xBAAB, and vice versa. The PWRM register only monitors DV_DD power failure. AV_CC is monitored by the analog reset circuit. When there is a power failure on AV_CC all the DACs in the device go into clear state.

7.6.8 SDIV Register (address = 0x9) [reset = 0x0000]

Figure 48. SDIV Register

15	14	13	12	11	10	9	8
Reserved
R/W

7	6	5	4	3	2	1	0
Reserved					SDIV
R/W					R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. SDIV Register

Bit	Field	Type	Reset	Description
15:3	Reserved	R/W	0000	Not Used
2:0	SDIV	R/W	000	Status signal toggle rate: STATS pin toggling rate is controlled by SDIV register. SDIV is valid between 0 and 6. The STATS pin toggles on every 2^SDIV trigger pulse. The SDIV setting should only be updated after a device reset and before configuring the DAC outputs.