For a single update, the DACx0501 requires a start condition, a valid I²C address byte, a command byte, and two data bytes: the most significant data byte (MSDB), and least significant data byte (LSDB), as listed in Table 8-1.

After each byte is received, the DACx0501 acknowledge the byte by pulling the SDA line low during the high period of a single clock pulse, as shown in Figure 8-7. These four bytes and acknowledge cycles make up the 36 clock cycles required for a single update to occur. A valid I²C address byte selects the DACx0501 devices.

Figure 8-7 I²C Bus Protocol

The command byte sets the operational mode of the selected DACx0501 device. When the operational mode is selected by this byte, the DACx0501 must receive two data bytes, the most significant data byte (MSDB) and least significant data byte (LSDB), for a data update to occur. The DACx0501 devices perform an update on the falling edge of the acknowledge signal that follows the LSDB.

When using fast mode (clock = 400 kHz), the maximum DAC update rate is limited to 11.11 kSPS. Using the fast-mode plus (clock = 1 MHz), the maximum DAC update rate is limited to 27.77 kSPS. When a stop condition is received, the DACx0501 release the I²C bus and await a new start condition.