8.3.3.1 Power-on-Reset (POR)

The DACx0504 includes a power-on reset function that controls the output voltage at power up. After the V_DD and V_IO supplies have been established a POR event is issued. The POR causes all registers to initialize to their default values and communication with the device is valid only after a 250 µs power-on-reset delay. The default value for all DACs is either zero-code or midscale-code as determined by the RSTSEL pin. Each DAC channel remains at the power-up voltage until a valid command is written to it.

The POR circuit requires specific supply levels to discharge the internal capacitors and to reset the device on power up, as indicated in Figure 59 and Figure 60. In order to initiate a POR event, V_DD or V_IO must be below their corresponding low thresholds for at least 100 µs. If V_DD and V_IO remain above their specified high threshold a POR event will not occur. When the supplies drop below their high threshold but remain over the lower one (shown as the undefined region), the device may or may not reset under all specified temperature and power-supply conditions.

Figure 59. Threshold Levels for V_DD POR Circuit

Figure 60. Threshold Levels for V_IO POR Circuit