8.4.1 Stand-Alone Operation

A serial interface access cycle is initiated by asserting the CS pin low. The serial clock SCLK can be a continuous or gated clock. SDI data are clocked on SCLK falling edges. A regular serial interface access cycle is 24 bits long with error checking disabled and 32 bits long with error checking enabled, thus the CS pin must stay low for at least 24 or 32 SCLK falling edges. The access cycle ends when the CS pin is de-asserted high. If the access cycle contains less than the minimum clock edges, the communication is ignored. If the access cycle contains more than the minimum clock edges are present, only the last 24 or 32 bits are used by the device. When CS is high, the SCLK and SDI signals are blocked and the SDO pin is in a Hi-Z state.

In an error checking disabled access cycle (24-bits long) the first byte input to SDI is the instruction cycle which identifies the request as a read or write command and the 4-bit address to be accessed. The following bits in the cycle form the data cycle, as shown in Table 2.

A read operation is initiated by issuing a read command access cycle. After the read command, a second access cycle must be issued to get the requested data, as shown in Table 3. Data are clocked out on SDO pin either on the falling edge or rising edge of SCLK according to the FSDO bit in the CONFIG register.