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ZHCSH59C August 2017 – January 2019 DAC60504 , DAC70504 , DAC80504

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

RTE|16
- MPQF149D

散热焊盘机械数据 (封装 | 引脚)

RTE|16
- QFND298F

订购信息

8.5 Programming

The DACx0504 is controlled through a flexible four-wire serial interface that is compatible with SPI type interfaces used on many microcontrollers and DSP controllers. The interface provides read and write access to all DACx0504 registers and can also be configured to daisy-chain multiple devices for write operations. The DACx0504 incorporates an optional error checking mode to validate SPI data communication integrity in noisy environments. Table 7 shows the SPI timing requirements. Figure 62 and Figure 63 show the SPI write and read timing diagrams, respectively. Figure 64 shows the digital logic timing diagram.

Table 7. Programming Timing Requirements⁽¹⁾

		V_IO = 1.7 V to 2.7 V			V_IO = 2.7 V to 5.5 V			UNIT
		MIN	NOM	MAX	MIN	NOM	MAX	UNIT
SERIAL INTERFACE – WRITE OPERATION
f_SCLK	SCLK frequency			50			50	MHz
t_SCLKHIGH	SCLK high time	9			9			ns
t_SCLKLOW	SCLK low time	9			9			ns
t_SDIS	SDI setup	5			5			ns
t_SDIH	SDI hold	10			10			ns
t_CSS	CS to SCLK falling edge setup	13			13			ns
t_CSH	SCLK falling edge to CS rising edge	10			10			ns
t_CSHIGH	CS high time	15			15			ns
t_CSIGNORE	SCLK falling edge to CS ignore	7			7			ns
SERIAL INTERFACE – READ AND DAISY CHAIN OPERATION, FSDO = 0
f_SCLK	SCLK frequency			12			18	MHz
t_SCLKHIGH	SCLK high time	35			25			ns
t_SCLKLOW	SCLK low time	35			25			ns
t_SDIS	SDI setup	5			5			ns
t_SDIH	SDI hold	10			10			ns
t_CSS	CS to SCLK falling edge setup	32			20			ns
t_CSH	SCLK falling edge to CS rising edge	10			10			ns
t_CSHIGH	CS high time	15			15			ns
t_SDODLY	SDO output delay from SCLK rising edge	3.5		33.5	3.5		23	ns
t_SDODZ	SDO driven to tri-state	0		30	0		25	ns
t_CSIGNORE	SCLK falling edge to CS ignore	7			7			ns
SERIAL INTERFACE – READ AND DAISY CHAIN OPERATION, FSDO = 1
f_SCLK	SCLK frequency			20			25	MHz
t_SCLKHIGH	SCLK high time	22			18			ns
t_SCLKLOW	SCLK low time	22			18			ns
t_SDIS	SDI setup	5			5			ns
t_SDIH	SDI hold	10			10			ns
t_CSS	CS to SCLK falling edge setup	32			20			ns
t_CSH	SCLK falling edge to CS rising edge	10			10			ns
t_CSHIGH	CS high time	15			15			ns
t_SDODLY	SDO output delay from SCLK falling edge	3.5		45	3.5		32	ns
t_SDODZ	SDO driven to tri-state	0		30	0		25	ns
t_CSIGNORE	SCLK falling edge to CS ignore	7			7			ns
DIGITAL LOGIC
t_RSTDLYPOR	POR reset delay		170	250		170	250	µs
t_DACWAIT	Sequential DAC output updates	1			1			µs
t_LDACS	LDAC setup	0			0			ns
t_LDACH	LDAC hold	5			5			ns

(1) All input signals are specified at t_R = t_F = 1 ns/V (10% to 90% of V_IO), timed from a voltage level of (V_IL + V_IH) / 2, V_DD = 2.7 V to 5.5 V, V_IO = 1.7 V to 5.5 V, V_REFIN = 1.25 V to 5.5 V, SDO loaded with 20 pF, and T_A = –40°C to +125°C (unless otherwise noted)

DAC80504 DAC70504 DAC60504 dac80504-serial-interface-write-timing.gif

Figure 62. Serial Interface Write Timing Diagram

DAC80504 DAC70504 DAC60504 dac80504-serial-interface-read-timing.gif

Figure 63. Serial Interface Read Timing Diagram

DAC80504 DAC70504 DAC60504 dac80504-digital-logic-timing-diagram.gif

Figure 64. Digital Logic Timing Diagram