ZHCSIG8A July   2018  – November 2018 DAC61408 , DAC71408 , DAC81408

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      功能方框图
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Digital-to-Analog Converters (DACs) Architecture
        1. 9.3.1.1 DAC Transfer Function
        2. 9.3.1.2 DAC Register Structure
          1. 9.3.1.2.1 DAC Register Synchronous and Asynchronous Updates
          2. 9.3.1.2.2 Broadcast DAC Register
          3. 9.3.1.2.3 Clear DAC Operation
      2. 9.3.2 Internal Reference
      3. 9.3.3 Device Reset Options
        1. 9.3.3.1 Power-on-Reset (POR)
        2. 9.3.3.2 Hardware Reset
        3. 9.3.3.3 Software Reset
      4. 9.3.4 Thermal Protection
        1. 9.3.4.1 Analog Temperature Sensor: TEMPOUT Pin
        2. 9.3.4.2 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Toggle Mode
      2. 9.4.2 Differential Mode
      3. 9.4.3 Power-Down Mode
    5. 9.5 Programming
      1. 9.5.1 Stand-Alone Operation
        1. 9.5.1.1 Streaming Mode Operation
      2. 9.5.2 Daisy-Chain Operation
      3. 9.5.3 Frame Error Checking
    6. 9.6 Register Maps
      1. 9.6.1  NOP Register (Offset = 00h) [reset = 0000h]
        1. Table 9. NOP Register Field Descriptions
      2. 9.6.2  DEVICEID Register (Offset = 01h) [reset = ----h]
        1. Table 10. DEVICEID Register Field Descriptions
      3. 9.6.3  STATUS Register (Offset = 02h) [reset = 0000h]
        1. Table 11. STATUS Register Field Descriptions
      4. 9.6.4  SPICONFIG Register (Offset = 03h) [reset = 0A24h]
        1. Table 12. SPICONFIG Register Field Descriptions
      5. 9.6.5  GENCONFIG Register (Offset = 04h) [reset = 7F00h]
        1. Table 13. GENCONFIG Register Field Descriptions
      6. 9.6.6  BRDCONFIG Register (Offset = 05h) [reset = FFFFh]
        1. Table 14. BRDCONFIG Register Field Descriptions
      7. 9.6.7  SYNCCONFIG Register (Offset = 06h) [reset = 0000h]
        1. Table 15. SYNCCONFIG Register Field Descriptions
      8. 9.6.8  TOGGCONFIG0 Register (Offset = 07h) [reset = 0000h]
        1. Table 16. TOGGCONFIG0 Register Field Descriptions
      9. 9.6.9  TOGGCONFIG1 Register (Offset = 08h) [reset = 0000h]
        1. Table 17. TOGGCONFIG1 Register Field Descriptions
      10. 9.6.10 DACPWDWN Register (Offset = 09h) [reset = FFFFh]
        1. Table 18. DACPWDWN Register Field Descriptions
      11. 9.6.11 DACRANGEn Register (Offset = 0Bh - 0Ch) [reset = 0000h]
        1. Table 19. DACRANGEn Register Field Descriptions
      12. 9.6.12 TRIGGER Register (Offset = 0Eh) [reset = 0000h]
        1. Table 20. TRIGGER Register Field Descriptions
      13. 9.6.13 BRDCAST Register (Offset = 0Fh) [reset = 0000h]
        1. Table 21. BRDCAST Register Field Descriptions
      14. 9.6.14 DACn Register (Offset = 14h - 1Bh) [reset = 0000h]
        1. Table 22. DACn Register Field Descriptions
      15. 9.6.15 OFFSETn Register (Offset = 21h - 22h) [reset = 0000h]
        1. Table 23. OFFSETn Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure for Remote Ground Tracking
        1. 10.2.2.1 Generating 300mV Offset
        2. 10.2.2.2 Amplifier Selection
        3. 10.2.2.3 Passive Component Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 文档支持
    2. 13.2 相关链接
    3. 13.3 接收文档更新通知
    4. 13.4 社区资源
    5. 13.5 商标
    6. 13.6 静电放电警告
    7. 13.7 术语表
  14. 14机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5 Electrical Characteristics

all minimum/maximum specifications at TA = -40℃ to +125℃ and all typical specifications at TA = 25℃, VCC = 9 V to 41.5 V, VSS = -21.5 V to 0 V, VDD = VAA = 4.5 V to 5.5 V, VREFIN = 2.5 V, VIO = 1.7 V to 5.5 V, DAC outputs unloaded, Digital inputs at VIO or GND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE(1)
DAC81408 Resolution 16 Bits
Integral nonlinearity (INL) All ranges, except 0 to 40 V and ±2.5 V -1 ±0.5 1 LSB
0 to 40 V and ±2.5 V range -2 ±1 2 LSB
Differential nonlinearity (DNL) Specified 16-bit monotonic -1 ±0.5 1 LSB
DAC71408 Resolution 14 Bits
Integral nonlinearity (INL) All ranges -1 ±0.5 1 LSB
Differential nonlinearity (DNL) Specified 14-bit monotonic -1 ±0.5 1 LSB
DAC61408 Resolution 12 Bits
Integral nonlinearity (INL) All ranges -1 ±0.5 1 LSB
Differential nonlinearity (DNL) Specified 12-bit monotonic -1 ±0.5 1 LSB
TUE Total unadjusted error All ranges, except ±2.5 V -0.1 ±0.01 0.1 %FSR
±2.5 V range -0.2 ±0.02 0.2
Unipolar offset error All unipolar ranges -0.03 ±0.015 0.03 %FSR
Unipolar zero-code error All unipolar ranges 0 0.04 0.1 %FSR
Bipolar zero error All bipolar ranges -0.2 ±0.02 0.2 %FSR
Full-scale error All ranges -0.2 ±0.075 0.2 %FSR
Gain error All ranges, except ±2.5 V -0.1 ±0.02 0.1 %FSR
±2.5 V range -0.2 ±0.02 0.2
Unipolar offset error drift All unipolar ranges ±2 ppm of FSR/°C
Bipolar zero error drift All bipolar ranges ±2 ppm of FSR/°C
Gain error drift All ranges ±2 ppm of FSR/°C
Output voltage drift over time TA = 40°C, Full-scale code, 1900 hours 5 ppm of FSR
DIFFERENTIAL MODE PERFORMANCE(1)
TUE Total unadjusted error All ranges -0.1 ±0.01 0.1 %FSR
±2.5 V range -0.2 ±0.02 0.2
Common mode error All bipolar ranges. Midscale code -0.1 ±0.01 0.1 %FSR
OUTPUT CHARACTERISTICS
Output voltage headroom to VSS and VCC
(-10 mA ≤ IOUT ≤ 10 mA) 		 1 V
to VSS and VCC
(-15 mA ≤ IOUT ≤ 15 mA)		 1.5
Short circuit current(2) Full-scale output shorted to VSS 40 mA
Zero-scale output shorted to VCC 40
Load regulation Midscale code, -15 mA ≤ IOUT ≤ 15 mA 70 μV/mA
Maximum capacitive load(3) RLOAD = open 0 1 nF
DC output impedance Midscale code 0.05 Ω
Full-scale code 40
DYNAMIC PERFORMANCE
Output voltage settling time ¼ to ¾ scale and ¾ to ¼ scale settling time to ±1 LSB, ±10 V range,
RL = 5 kΩ, CL = 200 pF		 12 µs
Slew rate 0 to 5 V range 1 V/µs
All other output ranges 4
Power-on glitch magnitude Power-down to active DAC output.
±20 V range, midscale code,
RL = 5 kΩ, CL = 200 pF		 0.3 V
Output noise 0.1 Hz to 10 Hz, midscale code,
0 to 5 V range		 15 µVpp
Output noise density 1 kHz, midscale code, 0 to 5 V range 78 nV/Hz
AC PSRR Midscale code, frequency = 60 Hz, amplitude 200 mVpp superimposed on VDD, VCC or VSS 1 LSB/V
DC PSRR Midscale code, VDD = 5 V ± 5%,
VCC = 20 V, VSS = -20 V		 1 LSB/V
Midscale code, VDD = 5 V,
VCC = 20 V ± 5%, VSS = -20 V		 1
Midscale code, VDD = 5 V, VCC = 20 V, VSS = -20 V ± 5% 1
Code change glitch impulse 1 LSB change around major carrier,
0 to 5 V range		 4 nV-s
Channel to Channel AC crosstalk 0 to 5 V range. Measured channel at midscale. Full-scale swing on all other channels 4 nV-s
Channel to Channel DC crosstalk 0 to 5 V range. Measured channel at midscale. All other channels at full-scale 0.25 LSB
Digital feedthrough 0 to 5 V range. Midscale code,
fSCLK = 1 MHz		 1 nV-s
EXTERNAL REFERENCE INPUT
VREFIN Reference input voltage range to VREFGND 2.49 2.5 2.51 V
Reference input current 50 µA
Reference input impedance 50 kΩ
Reference input capacitance 20 pF
INTERNAL REFERENCE
VREFOUT Reference output voltage range TA = 25°C 2.4975 2.5025 V
Reference output drift 5 15 ppm/°C
Reference output impedance 0.1 Ω
Reference output noise 0.1 Hz to 10 Hz 12 µVpp
Reference output noise density 10 kHz, REFLOAD = 10 nF 150 nV/Hz
Reference load current 5 mA
Reference load regulation Source 80 µV/mA
Reference line regulation 20 µV/V
Reference output drift over time TA = 25°C, 1900 hours 250 µV
Reference thermal hysteresis First cycle ±700 µV
Additional cycle ±50
DIGITAL INPUTS AND OUTPUTS
VIH High-level input voltage 0.7 × VIO V
VIL Low-level input voltage 0.3 × VIO V
Input current ±2 µA
Input pin capacitance 2 pF
VOH High-level output voltage IOH = 0.2 mA VIO - 0.2 V
VOL Low-level output voltage IOL = 0.2 mA 0.4 V
Output pin capacitance 5 pF
ALARM OUTPUT
Output pin capacitance 5 pF
VOL Low-level output voltage ILOAD = -0.2 mA 0.4 V
TEMPERATURE OUTPUT
VTEMPOUT,0C Output voltage offset at 0℃ 1.34 V
Sensor gain -4 mV/°C
POWER REQUIREMENTS
IDD VDD supply current Active mode. Internal reference enabled. Full-scale code. ±20 V output range. SPI static. 0.05 0.5 mA
Active mode. Internal reference disabled. Full-scale code. ±20 V output range. SPI static. 0.05 0.5 mA
Power-down mode 0.05 0.5 mA
IAA VAA supply current Active mode. Internal reference enabled. Full-scale code. ±20 V output range. SPI static. 20 30 mA
Active mode. Internal reference disabled. Full-scale code. ±20 V output range. SPI static. 18 28 mA
Power-down mode 2 85 µA
ICC VCC supply current Active mode. Internal reference enabled. Full-scale code. ±20 V output range. SPI static. 5 10 mA
Active mode. Internal reference disabled. Full-scale code. ±20 V output range. SPI static. 5 10 mA
Power-down mode 10 30 µA
 ISS VSS supply current Active mode. Internal reference enabled. Full-scale code. ±20 V output range. SPI static. -10 -5 mA
Active mode. Internal reference disabled. Full-scale code. ±20 V output range. SPI static. -10 -5 mA
Power-down mode -30 -10 µA
IIO VIO supply current SCLK and SDI toggling at 50 MHz 350 500 µA
(1) End point fit between codes. 16-bit: Code 256 to 65280, 14-bit: Code 128 to 16256, 12-bit: Code 32 to 4064.
(2) Temporary overload condition protection. Junction temperature can be exceeded during current limit. Operation above the specified maximum junction temperature may impair device reliability.
(3) Specified by design and characterization, not production tested.
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