Each DAC pair in the device, can be independently configured to operate as a differential output pair. The differential output of a DACx-y pair is updated by writing to the DACx channel. For proper operation, the two DAC pairs must be configured to the same output range prior to enabling differential mode. Figure 8-2 and Figure 8-3 show the ideal differential output voltages (V_DIFF) and common mode voltages (V_CM) for a DAC differential pair configured for ±20-V and 0 to 40-V operation, respectively.

After being configured as a differential output, the DACx-y pair can be set for toggle operation by updating the DACx toggle registers as described in Section 8.4.1.

Imbalances between the two differential signals result in common-mode and amplitude errors. The device incorporates an offset register that enables the user to introduce a voltage offset to the DACy channel of the DACx-y differential pair to compensate for a DC offset error between the two channels. The offset compensation gives approximately a ±0.2%FSR adjustment window. The differential DAC data register must be rewritten after an update to the offset register.

Figure 8-2 Differential Bipolar Output (16-Bit):
±20-V Output Range

Figure 8-3 Differential Unipolar Output (16-Bit):
0-V to 40-V Output Range