ZHCSIG7B July 2018 – June 2021 DAC61416 , DAC71416 , DAC81416
PRODUCTION DATA
The DAC outputs are set in clear mode through the CLR pin. In clear mode each DAC data channel is set to the clear code associated with its configuration as shown in Table 8-1. A CLR pin logic low forces all DAC channels to clear the contents of their buffer and active registers to the clear code, and sets the analog outputs accordingly regardless of their synchronization setting.
| UNIPOLAR / BIPOLAR RANGE | DIFFERENTIAL MODE | CLEAR CODE |
|---|---|---|
| Unipolar | No | Zero code |
| Unipolar | Yes | Midscale code |
| Bipolar | No | Midscale code |
| Bipolar | Yes | Midscale code |
When a DAC is operating in toggle mode, a clear command sets both toggle registers to the clear value.