ZHCSIG7B July   2018  – June 2021 DAC61416 , DAC71416 , DAC81416

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 8.3.1.1 DAC Transfer Function
        2. 8.3.1.2 DAC Register Structure
          1. 8.3.1.2.1 DAC Register Synchronous and Asynchronous Updates
          2. 8.3.1.2.2 Broadcast DAC Register
          3. 8.3.1.2.3 Clear DAC Operation
      2. 8.3.2 Internal Reference
      3. 8.3.3 Device Reset Options
        1. 8.3.3.1 Power-on-Reset (POR)
        2. 8.3.3.2 Hardware Reset
        3. 8.3.3.3 Software Reset
      4. 8.3.4 Thermal Protection
        1. 8.3.4.1 Analog Temperature Sensor: TEMPOUT Pin
        2. 8.3.4.2 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Toggle Mode
      2. 8.4.2 Differential Mode
      3. 8.4.3 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Stand-Alone Operation
        1. 8.5.1.1 Streaming Mode Operation
      2. 8.5.2 Daisy-Chain Operation
      3. 8.5.3 Frame Error Checking
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 术语表
  13. 13Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RHA|40
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
SERIAL INTERFACE - WRITE OPERATION
f(SCLK) Serial clock frequency VIO = 1.7 V to 2.7 V 25 MHz
VIO = 2.7 V to 5.5 V 50
tSCLKHIGH SCLK high time VIO = 1.7 V to 2.7 V 20 ns
VIO = 2.7 V to 5.5 V 10
tSCLKLOW SCLK low time VIO = 1.7 V to 2.7 V 20 ns
VIO = 2.7 V to 5.5 V 10
tSDIS SDI setup time VIO = 1.7 V to 2.7 V 10 ns
VIO = 2.7 V to 5.5 V 5
tSDIH SDI hold time VIO = 1.7 V to 2.7 V 10 ns
VIO = 2.7 V to 5.5 V 5
tCSS CS to SCLK falling edge setup time VIO = 1.7 V to 2.7 V 30 ns
VIO = 2.7 V to 5.5 V 15
tCSH SCLK falling edge to CS rising edge VIO = 1.7 V to 2.7 V 10 ns
VIO = 2.7 V to 5.5 V 5
tCSHIGH CS hight time VIO = 1.7 V to 2.7 V 50 ns
VIO = 2.7 V to 5.5 V 25
tDACWAIT Sequential DAC update wait time VIO = 1.7 V to 2.7 V 2.4 µs
VIO = 2.7 V to 5.5 V 2.4
tBCASTWAIT Broadcast DAC update wait time VIO = 1.7 V to 2.7 V 4 µs
VIO = 2.7 V to 5.5 V 4
SERIAL INTERFACE - READ AND DAISY CHAIN OPERATION, FSDO = 0
f(SCLK) Serial clock frequency VIO = 1.7 V to 2.7 V 15 MHz
VIO = 2.7 V to 5.5 V 20
tSCLKHIGH SCLK high time VIO = 1.7 V to 2.7 V 33 ns
VIO = 2.7 V to 5.5 V 25
tSCLKLOW SCLK low time VIO = 1.7 V to 2.7 V 33 ns
VIO = 2.7 V to 5.5 V 25
tSDIS SDI setup time VIO = 1.7 V to 2.7 V 10 ns
VIO = 2.7 V to 5.5 V 5
tSDIH SDI hold time VIO = 1.7 V to 2.7 V 10 ns
VIO = 2.7 V to 5.5 V 5
tCSS CS to SCLK falling edge setup time VIO = 1.7 V to 2.7 V 30 ns
VIO = 2.7 V to 5.5 V 20
tCSH SCLK falling edge to CS rising edge VIO = 1.7 V to 2.7 V 8 ns
VIO = 2.7 V to 5.5 V 5
tCSHIGH CS high time VIO = 1.7 V to 2.7 V 50 ns
VIO = 2.7 V to 5.5 V 25
tSDOZD SDO tri-state to driven VIO = 1.7 V to 2.7 V 0 20 ns
VIO = 2.7 V to 5.5 V 0 20
tSDODLY SDO output delay VIO = 1.7 V to 2.7 V 0 35 ns
VIO = 2.7 V to 5.5 V 0 20
SERIAL INTERFACE - READ AND DAISY CHAIN OPERATION, FSDO = 1
f(SCLK) Serial clock frequency VIO = 1.7 V to 2.7 V 25 MHz
VIO = 2.7 V to 5.5 V 35
tSCLKHIGH SCLK high time VIO = 1.7 V to 2.7 V 20 ns
VIO = 2.7 V to 5.5 V 14
tSCLKLOW SCLK low time VIO = 1.7 V to 2.7 V 20 ns
VIO = 2.7 V to 5.5 V 14
tSDIS SDI setup time VIO = 1.7 V to 2.7 V 10 ns
VIO = 2.7 V to 5.5 V 5
tSDIH SDI hold time VIO = 1.7 V to 2.7 V 10 ns
VIO = 2.7 V to 5.5 V 5
tCSS CS to SCLK falling edge setup time VIO = 1.7 V to 2.7 V 30 ns
VIO = 2.7 V to 5.5 V 20
tCSH SCLK falling edge to CS rising edge VIO = 1.7 V to 2.7 V 8 ns
VIO = 2.7 V to 5.5 V 5
tCSHIGH CS high time VIO = 1.7 V to 2.7 V 50 ns
VIO = 2.7 V to 5.5 V 25
tSDOZD SDO tri-state to driven VIO = 1.7 V to 2.7 V 0 20 ns
VIO = 2.7 V to 5.5 V 0 20
tSDODLY SDO output delay VIO = 1.7 V to 2.7 V 0 35 ns
VIO = 2.7 V to 5.5 V 0 20
DIGITAL LOGIC
tLOGDLY CS rising edge to LDAC or CLR falling edge delay time VIO = 1.7 V to 2.7 V 40 ns
tLOGDLY CS rising edge to LDAC or CLR falling edge delay time VIO = 2.7 V to 5.5 V 20
tLDAC LDAC low time VIO = 1.7 V to 2.7 V 20 ns
VIO = 2.7 V to 5.5 V 10
tCLR CLR low time VIO = 1.7 V to 2.7 V 20 ns
VIO = 2.7 V to 5.5 V 10
tRESET POR reset delay VIO = 1.7 V to 2.7 V 1 ms
VIO = 2.7 V to 5.5 V 1
fTOGGLE TOGGLE frequency VIO = 1.7 V to 2.7 V 100 kHz
VIO = 2.7 V to 5.5 V 100
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