ZHCSSI1D august 2008 – august 2023 DAC5311 , DAC6311 , DAC7311
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Device Comparison
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics
- 7.6 Timing Requirements
- 7.7 Timing Diagrams
- 7.8 Typical Characteristics: AVDD = 5 V
- 7.9 Typical Characteristics: AVDD = 3.6 V
- 7.10 Typical Characteristics: AVDD = 2.7 V
- 8 Detailed Description
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
6 Pin Configuration and Functions
Figure 6-1 DCK Package, 6-Pin SC70 (Top
View)Table 6-1 Pin Functions
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| AVDD/VREF | 4 | Input | Power supply input, 2.0 V to 5.5 V. |
| DIN | 3 | Input | Serial Data Input. Data are clocked into the 16-bit input shift register on the falling edge of the serial clock input. |
| GND | 5 | — | Ground reference point for all circuitry on the part. |
| SCLK | 2 | Input | Serial clock input. Data are transferred at rates up to 50 MHz. |
| SYNC | 1 | Input | Level-triggered control input (active low). This pin is the frame synchronization signal for the input data. When SYNC goes low, the input shift register is enabled and data are transferred in on the falling edges of the following clocks. The DAC is updated following 16th clock cycle, unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DACx311. See the SYNC Interrupt section for more details. |
| VOUT | 6 | Output | Analog output voltage from DAC. The output amplifier has rail-to-rail operation. |