Table 7-14 shows that for a single update, the DAC63202W require a start condition, a valid I²C address byte, a command byte, and two data bytes.

Figure 7-23 shows that after each byte is received, the DAC63202W family acknowledges the byte by pulling the SDA line low during the high period of a single clock pulse. These four bytes and acknowledge cycles make up the 36 clock cycles required for a single update to occur. A valid I²C address byte selects the DAC63202W.

The command byte sets the operating mode of the selected DAC63202W device. For a data update to occur when the operating mode is selected by this byte, the DAC63202W device must receive two data bytes: the most significant data byte (MSDB) and least significant data byte (LSDB). The DAC63202W device performs an update on the falling edge of the acknowledge signal that follows the LSDB.

When using fast mode (clock = 400 kHz), the maximum DAC update rate is limited to 10 kSPS. Using fast mode plus (clock = 1 MHz), the maximum DAC update rate is limited to 25 kSPS. When a stop condition is received, the DAC63202W device releases the I²C bus and awaits a new start condition.