ZHCSRX3 april   2023 DAC63202W

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: Current Output
    7. 6.7  Electrical Characteristics: Comparator Mode
    8. 6.8  Electrical Characteristics: General
    9. 6.9  Timing Requirements: I2C Standard Mode
    10. 6.10 Timing Requirements: I2C Fast Mode
    11. 6.11 Timing Requirements: I2C Fast Mode Plus
    12. 6.12 Timing Requirements: SPI Write Operation
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    14. 6.14 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    15. 6.15 Timing Requirements: GPIO
    16. 6.16 Timing Diagrams
    17. 6.17 Typical Characteristics: Voltage Output
    18. 6.18 Typical Characteristics: Current Output
    19. 6.19 Typical Characteristics: Comparator
    20. 6.20 Typical Characteristics: General
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Digital-to-Analog Converter (DAC) Architecture
      2. 7.3.2 Digital Input/Output
      3. 7.3.3 Nonvolatile Memory (NVM)
    4. 7.4 Device Functional Modes
      1. 7.4.1 Voltage-Output Mode
        1. 7.4.1.1 Voltage Reference and DAC Transfer Function
          1. 7.4.1.1.1 Internal Reference
          2. 7.4.1.1.2 External Reference
          3. 7.4.1.1.3 Power-Supply as Reference
      2. 7.4.2 Current-Output Mode
      3. 7.4.3 Comparator Mode
        1. 7.4.3.1 Programmable Hysteresis Comparator
        2. 7.4.3.2 Programmable Window Comparator
      4. 7.4.4 Fault-Dump Mode
      5. 7.4.5 Application-Specific Modes
        1. 7.4.5.1 Voltage Margining and Scaling
          1. 7.4.5.1.1 High-Impedance Output and PROTECT Input
          2. 7.4.5.1.2 Programmable Slew-Rate Control
          3. 7.4.5.1.3 PMBus Compatibility Mode
        2. 7.4.5.2 Function Generation
          1. 7.4.5.2.1 Triangular Waveform Generation
          2. 7.4.5.2.2 Sawtooth Waveform Generation
          3. 7.4.5.2.3 Sine Waveform Generation
      6. 7.4.6 Device Reset and Fault Management
        1. 7.4.6.1 Power-On Reset (POR)
        2. 7.4.6.2 External Reset
        3. 7.4.6.3 Register-Map Lock
        4. 7.4.6.4 NVM Cyclic Redundancy Check (CRC)
          1. 7.4.6.4.1 NVM-CRC-FAIL-USER Bit
          2. 7.4.6.4.2 NVM-CRC-FAIL-INT Bit
      7. 7.4.7 Power-Down Mode
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
      3. 7.5.3 General-Purpose Input/Output (GPIO) Modes
    6. 7.6 Register Map
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-X-MARGIN-HIGH Register (address = 13h, 01h) [reset = 0000h]
      3. 7.6.3  DAC-X-MARGIN-LOW Register (address = 14h, 02h) [reset = 0000h]
      4. 7.6.4  DAC-X-VOUT-CMP-CONFIG Register (address = 15h, 03h) [reset = 0000h]
      5. 7.6.5  DAC-X-IOUT-MISC-CONFIG Register (address = 16h, 04h) [reset = 0000h]
      6. 7.6.6  DAC-X-CMP-MODE-CONFIG Register (address = 17h, 05h) [reset = 0000h]
      7. 7.6.7  DAC-X-FUNC-CONFIG Register (address = 18h, 06h) [reset = 0000h]
      8. 7.6.8  DAC-X-DATA Register (address = 1Ch, 19h) [reset = 0000h]
      9. 7.6.9  COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
      10. 7.6.10 COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      11. 7.6.11 COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
      12. 7.6.12 GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
      13. 7.6.13 CMP-STATUS Register (address = 23h) [reset = 0000h]
      14. 7.6.14 GPIO-CONFIG Register (address = 24h) [reset = 0000h]
      15. 7.6.15 DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
      16. 7.6.16 INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      17. 7.6.17 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      18. 7.6.18 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      19. 7.6.19 BRDCAST-DATA Register (address = 50h) [reset = 0000h]
      20. 7.6.20 PMBUS-PAGE Register [reset = 0300h]
      21. 7.6.21 PMBUS-OP-CMD-X Register [reset = 0000h]
      22. 7.6.22 PMBUS-CML Register [reset = 0000h]
      23. 7.6.23 PMBUS-VERSION Register [reset = 2200h]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information

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6.8 Electrical Characteristics: General

all minimum/maximum specifications at –40°C ≤ TA ≤ +125°C and typical specifications at TA = 25°C, 1.7 V ≤ VDD ≤ 5.5 V, DAC reference tied to VDD, gain = 1 × in voltage output mode or ±250-µA output range in current output mode, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) in voltage-output mode and capacitive load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INTERNAL REFERENCE
Initial accuracy TA = 25°C 1.1979 1.212 1.224 V
Reference output temperature coefficient(1) (2) 50 ppm/°C 
EXTERNAL REFERENCE
VREF input impedance(1) (3) 192 kΩ/ch
EEPROM
Endurance(1) –40°C ≤ TA ≤ +85°C  20000 Cycles
TA = 125°C  1000
Data retention(1) TA = 25°C  50 Years
EEPROM programming write cycle time(1) 200 ms
Device boot-up time(1) Time taken from power valid (VDD ≥ 1.7 V) to output valid state (output state as programmed in EEPROM), 0.5-µF capacitor on the CAP pin 5 ms
DIGITAL INPUTS
Digital feedthrough Voltage output mode, DAC output static at midscale, fast mode plus, SCL toggling 20 nV-s
IDD Current flowing into VDD DAC in sleep mode, internal reference powered down, external reference at 5.5 V 28 µA
IDD Current flowing into VDD(1) DAC in sleep mode, internal reference enabled, additional current through internal reference 10 µA
IDD Current flowing into VDD(1) DAC channels enabled, internal reference enabled, additional current through internal reference per DAC channel in voltage-output mode 12.5 µA
Pin capacitance Per pin 10 pF
POWER-DOWN MODE
HIGH-IMPEDANCE OUTPUT
ILEAK Current flowing into VOUTX and VFBX DAC in Hi-Z output mode, 1.7 V ≤ VDD ≤ 5.5 V 10 nA
VDD = 0 V, VOUT ≤ 1.5 V, decoupling capacitor between VDD and AGND = 0.1 μF 200 nA
VDD = 0 V, 1.5 V < VOUT ≤ 5.5 V, decoupling capacitor between VDD and AGND = 0.1 μF 500 nA
100 kΩ between VDD and AGND, VOUT ≤ 1.25 V, series resistance of 10 kΩ at OUT pin ±2 µA
(1) Specified by design and characterization, not production tested.
(2) Measured at –40°C and +125°C and calculated the slope.
(3) Impedances for the DAC channels are connected in parallel.
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