ZHCSRA2
December 2022
DAC53204W
,
DAC63204W
PRODUCTION DATA
1
特性
2
应用
3
说明
4
Revision History
5
Pin Configuration and Functions
6
规格
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics: Voltage Output
6.6
Electrical Characteristics: Current Output
6.7
Electrical Characteristics: Comparator Mode
6.8
Electrical Characteristics: General
6.9
Timing Requirements: I2C Standard Mode
6.10
Timing Requirements: I2C Fast Mode
6.11
Timing Requirements: I2C Fast Mode Plus
6.12
Timing Requirements: SPI Write Operation
6.13
Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
6.14
Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
6.15
Timing Requirements: GPIO
6.16
Timing Diagrams
6.17
Typical Characteristics: Voltage Output
6.18
Typical Characteristics: Current Output
6.19
Typical Characteristics: Comparator
6.20
Typical Characteristics: General
7
详细说明
7.1
Overview
7.2
Functional Block Diagram
7.3
特性说明
7.3.1
智能数模转换器 (DAC) 架构
7.3.2
数字输入/输出
7.3.3
Nonvolatile Memory (NVM)
7.4
器件功能模式
7.4.1
电压输出模式
7.4.1.1
电压基准和 DAC 传递函数
7.4.1.1.1
Internal Reference
7.4.1.1.2
External Reference
7.4.1.1.3
Power-Supply as Reference
7.4.2
Current-Output Mode
7.4.3
比较器模式
7.4.3.1
可编程迟滞比较器
7.4.3.2
Programmable Window Comparator
7.4.4
故障转储模式
7.4.5
应用特定模式
7.4.5.1
电压裕量和调节
7.4.5.1.1
高阻抗输出和 PROTECT 输入
7.4.5.1.2
Programmable Slew-Rate Control
7.4.5.1.3
PMBus Compatibility Mode
7.4.5.2
函数生成
7.4.5.2.1
Triangular Waveform Generation
7.4.5.2.2
Sawtooth Waveform Generation
7.4.5.2.3
Sine Waveform Generation
7.4.6
器件复位和故障管理
7.4.6.1
上电复位 (POR)
7.4.6.2
External Reset
7.4.6.3
Register-Map Lock
7.4.6.4
NVM 循环冗余校验 (CRC)
7.4.6.4.1
NVM-CRC-FAIL-USER 位
7.4.6.4.2
NVM-CRC-FAIL-INT 位
7.4.7
Power-Down Mode
7.5
编程
7.5.1
SPI 编程模式
7.5.2
I2C Programming Mode
7.5.2.1
F/S 模式协议
7.5.2.2
I2C 更新序列
7.5.2.2.1
地址字节
7.5.2.2.2
Command Byte
7.5.2.3
I2C 读取序列
7.5.3
通用输入/输出 (GPIO) 模式
7.6
Register Map
7.6.1
NOP Register (address = 00h) [reset = 0000h]
7.6.2
DAC-X-MARGIN-HIGH Register (address = 01h, 07h, 0Dh, 13h) [reset = 0000h]
7.6.3
DAC-X-MARGIN-LOW Register (address = 02h, 08h, 0Eh, 14h) [reset = 0000h]
7.6.4
DAC-X-VOUT-CMP-CONFIG Register (address = 03h, 09h, 0Fh, 15h) [reset = 0000h]
7.6.5
DAC-X-IOUT-MISC-CONFIG Register (address = 04h, 0Ah, 10h, 16h) [reset = 0000h]
7.6.6
DAC-X-CMP-MODE-CONFIG Register (address = 05h, 0Bh, 11h, 17h) [reset = 0000h]
7.6.7
DAC-X-FUNC-CONFIG Register (address = 06h, 0Ch, 12h, 18h) [reset = 0000h]
7.6.8
DAC-X-DATA Register (address = 19h, 1Ah, 1Bh, 1Ch) [reset = 0000h]
7.6.9
COMMON-CONFIG Register (address = 1Fh) [reset = 0FFFh]
7.6.10
COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
7.6.11
COMMON-DAC-TRIG Register (address = 21h) [reset = 0000h]
7.6.12
GENERAL-STATUS Register (address = 22h) [reset = 00h, DEVICE-ID, VERSION-ID]
7.6.13
CMP-STATUS 寄存器(地址 = 23h)[复位 = 0000h]
7.6.14
GPIO-CONFIG Register (address = 24h) [reset = 0000h]
7.6.15
DEVICE-MODE-CONFIG Register (address = 25h) [reset = 0000h]
7.6.16
INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
7.6.17
SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
7.6.18
SRAM-DATA Register (address = 2Ch) [reset = 0000h]
7.6.19
DAC-X-DATA-8BIT Register (address = 40h, 41h, 42h, 43h) [reset = 0000h]
7.6.20
BRDCAST-DATA Register (address = 50h) [reset = 0000h]
7.6.21
PMBUS-PAGE Register [reset = 0300h]
7.6.22
PMBUS-OP-CMD-X Register [reset = 0000h]
7.6.23
PMBUS-CML Register [reset = 0000h]
7.6.24
PMBUS-VERSION 寄存器 [复位 = 2200h]
8
应用和实现
8.1
Application Information
8.2
Typical Application
8.2.1
Design Requirements
8.2.2
Detailed Design Procedure
8.2.3
Application Curve
8.3
Power Supply Recommendations
8.4
布局
8.4.1
布局指南
8.4.2
Layout Example
9
器件和文档支持
9.1
Documentation Support
9.1.1
Related Documentation
9.2
接收文档更新通知
9.3
支持资源
9.4
商标
9.5
Electrostatic Discharge Caution
9.6
术语表
10
机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
YBH|16
MPBGAQ3
散热焊盘机械数据 (封装 | 引脚)
订购信息
zhcsra2_oa
7.3
特性说明
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