at TA = 25°C, VDD = 5.5 V,
output range: ±250 μA (unless otherwise noted)
Figure 6-31 Current Output INL vs Digital Input Code Figure 6-33 Current Output INL vs Supply Voltage Figure 6-35 Current Output DNL vs Temperature Figure 6-37 Current Output TUE vs Digital Input Code Figure 6-39 Current Output TUE vs Supply Voltage Figure 6-41 Current Output Gain Error vs Temperature Figure 6-43 Current Output Settling Time: Rising Edge (¼ to ¾ scale)
DAC
at mid scale (0 μA) stored in EEPROM |
Figure 6-45 Current Output Power-On Glitch
Channel 4 is resident, all other channels are
interferers |
Figure 6-47 Current Output Channel-to-Channel CrosstalkFigure 6-49 Current Output Noise Density Figure 6-32 Current Output INL vs Temperature Figure 6-34 Current Output DNL vs Digital Input Code Figure 6-36 Current Output DNL vs Supply Voltage Figure 6-38 Current Output TUE vs Temperature Figure 6-40 Current Output Offset Error vs Temperature Figure 6-42 Current Output vs Load Voltage Figure 6-44 Current Output Settling Time: Falling Edge (¾ to ¼ scale) Figure 6-46 Current Output Power-Off Glitch Figure 6-48 Current Output AC PSRR vs Frequency Figure 6-50 Current Output Flicker Noise