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ZHCSNR2A December 2021 – May 2024 DAC43508 , DAC53508 , DAC63508

PRODUCTION DATA

5.10 Typical Characteristics: Dynamic Performance

at T_A = 25°C, V_DD = 5.5 V, reference = 5.5 V, 12-bit resolution, and DAC outputs unloaded (unless otherwise noted)

DAC code transition from midscale – 4 LSB to midscale,
output load: 5 kΩ || 200 pF

Figure 5-36 Glitch Impulse, Rising Edge, 4-LSB Step

DAC code transition from 408d to 3688d, typical
channel shown, output load: 5 kΩ || 200 pF

Figure 5-38 Full-Scale Settling Time, Rising Edge


Output load: 5 kΩ \|\| 200 pF

Figure 5-40 Power-On Glitch

DAC at midscale, reference tied to V_DD,
output load: 5 kΩ || 200 pF, SCLK = 1 MHz

Figure 5-42 Clock Feedthrough


DAC at midscale, f = 0.1 Hz to 10 Hz

Figure 5-44 Flicker Noise

DAC code transition from midscale to midscale – 4 LSB,
output load: 5 kΩ || 200 pF

Figure 5-37 Glitch Impulse, Falling Edge, 4-LSB Step

DAC code transition from 3688d to 408d, typical
channel shown, output load: 5 kΩ || 200 pF

Figure 5-39 Full-Scale Settling Time, Falling Edge


Output load: 5 kΩ \|\| 200 pF

Figure 5-41 Power-Off Glitch

DAC at full-scale, output load: 5 kΩ || 200 pF,
V_DD = 5.25 V + 0.2 V_PP, V_REFIN = 4.5 V

Figure 5-43 AC Power-Supply Rejection Ratio vs Frequency

Figure 5-45 Noise Spectral Density