ZHCSEV4A February 2016 – March 2016 DAC8551-Q1
PRODUCTION DATA.
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| DIN | 7 | I | Serial data input. Data is clocked into the 24-bit input shift register on each falling edge of the serial clock input. Schmitt-trigger logic input. |
| GND | 8 | GND | Ground reference point for all circuitry on the device |
| SCLK | 6 | I | Serial clock input. Data can be transferred at rates up to 3 0MHz. Schmitt-trigger logic input. |
| SYNC | 5 | I | Level-triggered control input (active-low). This is the frame synchronization signal for the input data. SYNC going low enables the input shift register, and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock (unless SYNC is taken high before this edge, in which case the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by the DAC8551-Q1). Schmitt-trigger logic input. |
| VDD | 1 | PWR | Power supply input, 3.2 V to 5.5 V. |
| VFB | 3 | I | Feedback connection for the output amplifier. For voltage output operation, tie to VOUT externally. |
| VOUT | 4 | O | Analog output voltage from DAC. The output amplifier has rail-to-rail operation. |
| VREF | 2 | I | Reference voltage input. |