The output offset error of a sample-and-hold channel is the cumulative error contributed by the DAC offset error, amplifier offset error, and sample-and-hold pedestal error due to charge injection. The amplifier offset error can be made negligible by choosing a low-offset amplifier, such as the OPA4317. The OPA4317 has a maximum offset error of 0.1 mV. The DAC80501 has a maximum offset error of ±1.5 mV. Thus, to achieve a total offset error less than ±3 mV, limit the offset error contributed by the sample-and-hold circuit to ±1.5 mV.

Considering the bias current of 300 pA in the OPA4317, and a typical switch leakage current of 1 nA, a 2‑nF hold capacitor results in a droop rate of 0.65 V/s. When the sample-and-hold circuit refreshes at a rate of more than 100 µs, the voltage droop is 65 µV. This small offset error can be ignored for the simplicity of calculation. Thus, the only contributor to the sample-and-hold offset error is the pedestal error. For a charge injection of 3 pC and a pedestal error of 1.5 mV, the value of the hold capacitor is calculated as 2 nF, according to Equation 2. A capacitive load of 2 nF can be handled by the DAC80501. The switch-on resistance and optional series resistance R_S further helps in the stability of the DAC output amplifier. R_S can be omitted for better settling time.