ZHCSJ19E november 2018 – august 2023 DAC60501 , DAC70501 , DAC80501
PRODUCTION DATA
The DACx0501 digital interface is programmed to work in SPI mode when the logic level of the SPI2C pin is 0 at power up. In SPI mode, the DACx0501 have a 3-wire serial interface: SYNC, SCLK, and SDIN, as shown in Section 6. The serial interface is compatible with SPI, QSPI, and Microwire interface standards, and most digital signal processors (DSPs). The serial interface operates at up to 50 MHz. The input shift register is 24 bits wide.
The serial clock SCLK is a continuous or a gated clock. The first falling edge of SYNC starts the operation cycle. When SYNC is high, the SCLK and SDIN signals are blocked. The device internal registers are updated from the shift register on the rising edge of SYNC.