ZHCSH59C August 2017 – January 2019 DAC60504 , DAC70504 , DAC80504
PRODUCTION DATA.
The reference voltage to the device, either from the internal reference or an external one can be divided by a factor of two by tying the REFDIV pin high at power-up or by setting the REF-DIV bit in the GAIN register to 1 during normal operation. The reference voltage divider provides additional flexibility in setting the full-scale output voltage for each DAC output and must be configured to make certain that there is sufficient headroom from VDD to the DAC operating reference voltage (VREF/DIV). See the Recommended Operating Conditions table for more information.
Improper configuration of the reference divider issues a reference alarm condition. In this case, the reference buffer is shut down, and all the DAC outputs go to 0 V. The DAC data registers are unaffected by the alarm condition thus enabling the DAC output to return to normal operation once the reference divider is configured correctly. The reference alarm status can be read from the REF-ALM bit in the STATUS register. Additionally by setting ALM-EN = 1 and ALM-SEL = 1 in the CONFIG register, the SDO/ALARM pin is configured as a reference alarm pin.