ZHCSH59C August 2017 – January 2019 DAC60504 , DAC70504 , DAC80504
PRODUCTION DATA.
If the DACx0504 is used in a noisy environment, error checking can be used to check the integrity of SPI data communication between the device and the host processor. This feature can be enabled by setting the CRC-EN bit in the CONFIG register.
The error checking scheme is based on the CRC-8-ATM (HEC) polynomial x8 + x2 + x + 1 (that is, 100000111). When error checking is enabled, the serial interface access cycle width is 32 bits. The normal 24-bit SPI data are appended with an 8-bit CRC polynomial by the host processor before feeding it to the device, as shown in Table 4. In all serial interface readback operations the CRC polynomial is output on the SDO pin as part of the 32-bit cycle.
| BIT | FIELD | DESCRIPTION |
|---|---|---|
| 31 | RW | Identifies the communication as a read or write command to the addressed register. R/W = 0 sets a write operation. R/W = 1 sets a read operation. |
| 30 | CRC-ERROR | Reserved bit. Set to zero. |
| 29:28 | Reserved | Reserved bits. Must be filled with zeros. |
| 27:24 | A[3:0] | Register address. Specifies the register to be accessed during the read or write operation. |
| 23:8 | DI[15:0] | Data cycle bits. If a write command, the data cycle bits are the values to be written to the register with address A[3:0]. If a read command, the data cycle bits are don’t care values. |
| 7:0 | CRC | 8-bit CRC polynomial. |
The DACx0504 decodes the 32-bit access cycle to compute the CRC remainder on CS rising edges. If no error exists, the CRC remainder is zero and data are accepted by the device.
A write operation failing the CRC check causes the data to be ignored by the device. After the write command, a second access cycle can be issued to determine the error checking result (CRC-ERROR bit) on the SDO pin, as shown in Table 5. Additionally, by setting ALM-EN = 1 and ALM-SEL = 0 in the CONFIG register, the SDO/ALARM pin is configured as a CRC alarm pin.
| BIT | FIELD | DESCRIPTION |
|---|---|---|
| 31 | RW | Echo RW from previous access cycle (RW = 0). |
| 30 | CRC-ERROR | Returns a 1 when a CRC error is detected, 0 otherwise. |
| 29:28 | Reserved | Echo bits 29:28 from previous access cycle (all zeros). |
| 27:24 | A[3:0] | Echo address from previous access cycle. |
| 23:8 | DO[15:0] | Echo data from previous access cycle. |
| 7:0 | CRC | Calculated CRC value of bits 31:8. |
A read operation must be followed by a second access cycle to get the requested data on the SDO pin. The error check result (CRC-ERROR bit) from the read command is output on the SDO pin, as shown in Table 6. As in the case of a write operation failing the CRC check, the SDO/ALARM pin if configured as a CRC alarm pin can be used to indicate a read command CRC failure.
| BIT | FIELD | DESCRIPTION |
|---|---|---|
| 31 | RW | Echo RW from previous access cycle (RW = 1). |
| 30 | CRC-ERROR | Returns a 1 when a CRC error is detected, 0 otherwise. |
| 29:28 | Reserved | Echo bits 29:28 from previous access cycle (all zeros). |
| 27:24 | A[3:0] | Echo address from previous access cycle. |
| 23:8 | DO[15:0] | Readback data requested on previous access cycle. |
| 7:0 | CRC | Calculated CRC value of bits 31:8. |