ZHCSH59C August 2017 – January 2019 DAC60504 , DAC70504 , DAC80504
PRODUCTION DATA.
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| REF | 1 | I/O | When using internal reference, this is the reference output voltage pin (default). When using an external reference, this is the reference input pin to the device. |
| OUT0 | 2 | O | Analog output voltage from DAC 0. |
| OUT1 | 3 | O | Analog output voltage from DAC 1. |
| OUT2 | 4 | O | Analog output voltage from DAC 2. |
| OUT3 | 5 | O | Analog output voltage from DAC 3. |
| GND | 6 | GND | Ground reference point for all circuitry on the device. |
| VDD | 7 | PWR | Analog supply voltage (2.7 V to 5.5 V). |
| GAIN | 8 | I | Sets the gain configuration after a power-up or reset event. When tied to GND, the initial buffer amplifier gain for all four channels is set to 1. When tied to VIO the initial buffer amplifier gain is 2. Changing the state of this pin after power-up does not affect the device operation. |
| RSTSEL | 9 | I | Reset select pin. When tied to GND all four DACs reset to zero scale. When connected to VIO all four DACs reset to midscale. |
| REFDIV | 10 | I | Sets the reference divider configuration after a power-up or reset event. When tied to GND, the reference voltage is not divided down. When tied to VIO the reference voltage is divided by 2. Changing the state of this pin after power-up does not affect the device operation. |
| LDAC | 11 | I | A high-to-low transition on the LDAC pin causes the DAC outputs of those channels configured in synchronous mode to update simultaneously. The pin can be tied permanently to GND. |
| CS | 12 | I | Active low serial data enable. This input is the frame synchronization signal for the serial data. When the signal goes low, it enables the serial interface input shift register. |
| SCLK | 13 | I | Serial interface clock. |
| SDI | 14 | I | Serial interface data input. Data are clocked into the input shift register on each falling edge of the SCLK pin. |
| SDO/ALARM | 15 | O | Serial interface data output (default). The SDO pin is in high impedance when CS pin is high. Data are clocked out of the input shift register on either rising or falling edges of the SCLK pin as specified by the FSDO bit. Alternatively the pin can be configured as an ALARM open-drain output to indicate a CRC or reference alarm event. If configured as ALARM a 10 kΩ, pull-up resistor to VIO is required. |
| VIO | 16 | PWR | IO supply voltage (1.7 V to 5.5 V). This pin sets the I/O operating voltage for the serial interface. |
| Thermal Pad | – | – | The thermal pad is located on the bottom-side of the QFN package. The thermal pad should be connected to any internal PCB ground plane using multiple vias for good thermal performance. |