ZHCS226B June   2011  – March 2015 DAC7551-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter
      2. 7.3.2 Resistor String
      3. 7.3.3 Output Buffer Amplifiers
        1. 7.3.3.1 DAC External Reference Input
        2. 7.3.3.2 Amplifier Sense Input
        3. 7.3.3.3 Power-On Reset
        4. 7.3.3.4 Power Down
        5. 7.3.3.5 Asynchronous Clear
        6. 7.3.3.6 IOVDD and Level Shifters
      4. 7.3.4 Integral and Differential Linearity
      5. 7.3.5 Glitch Energy
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 16-Bit Word and Input Shift Register
        2. 7.5.1.2 Daisy-Chain Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Waveform Generation
      2. 8.1.2 Generating ±5-V, ±10-V, and ±12-V Outputs For Precision Industrial Control
        1. 8.1.2.1 Loop Accuracy
        2. 8.1.2.2 Loop Speed
    2. 8.2 Typical Application
      1. 8.2.1 Generating Industrial Voltage Ranges
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 商标
    3. 11.3 静电放电警告
    4. 11.4 术语表
  12. 12机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

DRN Package
12-Pin USON With Exposed Thermal Pad
Top View
DAC7551-Q1 po_slas767.gif
1. The thermal pad should be connected to GND.

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 VDD I Analog voltage supply input
2 VREFH I Positive reference voltage input
3 VREFL I Negative reference voltage input
4 VFB I DAC amplifier sense input.
5 VOUT O Analog output voltage from DAC
6 GND — Ground.
7 CLR I Asynchronous input to clear the DAC registers. When the CLR pin is low, the DAC register is set to 000h and the output voltage to 0 V.
8 SYNC I Frame synchronization input. The falling edge of the SYNC pulse indicates the start of a serial data frame shifted out to the DAC7551-Q1 device.
9 SCLK I Serial clock input
10 SDIN I Serial data input
11 SDO O Serial data output
12 IOVDD I I/O voltage supply input
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |