Figure 8-5 illustrates an external NPN transistor used to reduce power dissipation on the die. Most of the load current flows through the NPN transistor with a small amount flowing through the on-chip PMOS transistor based on the gain of the NPN transistor. This configuration reduces the temperature induced drift on the die and internal reference and is an option for use cases at the extreme end of the supply, load current, and ambient temperature ranges.

The inclusion of the bipolar junction transistor (BJT) adds an additional open loop gain to internal amplifier A2 (see Figure 8-2) and thus, can cause possible instability. Adding series emitter resistor R2 decreases the gain of the stage created by the BJT and internal R3 resistor (see Figure 8-2) especially for cases where R_LOAD is a short or a very small load, such as a multimeter. Recommended values for R₁, R₂, and C₁ in this circuit are 1 kΩ, 30 Ω and 22 nF, respectively. An equivalent solution is to place R₂ (with a recommended value of 3 kΩ instead of 30 Ω) in series with the base of the transistor instead of the configuration provided in Figure 8-5. Note that there is some gain error introduced by this configuration; see Figure 7-14, Figure 7-15 and Figure 7-16. Use the internal transistor in most cases because the values in Section 7.5 are based on the configuration with the internal on-chip PMOS transistor.

Figure 8-5 Boost Mode Configuration