An external NPN transistor can be used as shown in Figure 8-6 to reduce power dissipation on the die. Most of the load current flows through the NPN transistor with a small amount flowing through the on-chip PMOS transistor based on the gain of the NPN transistor. This reduces the temperature induced drift on the die and internal reference and is an option for use cases at the extreme end of the supply, load current, and ambient temperature ranges. Resistor R₂ stabilizes this circuit for cases where the R_LOAD is a short or a very small load like a multimeter. Recommended values for R₁, R₂ and C₁ in this circuit are 1 kΩ, 20 Ω and 0.22 µF. An equivalent solution is to place R₂ (with a recommended value of 2 kΩ instead of the 20 Ω) in series with the base of the transistor instead of the configuration shown in Figure 8-6. Note that there is some gain error introduced by this configuration as seen in Figure 7-46 for the 0-mA to 24-mA range. TI recommends using the internal transistor in most cases as the values in Section 7.5 are based on the configuration with the internal on-chip PMOS transitor.

Figure 8-6 Boost Mode Configuration