ZHCSBX4D June   2013  – December 2021 DAC7760 , DAC8760

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Electrical Characteristics: AC
    7. 7.7  Timing Requirements: Write Mode
    8. 7.8  Timing Requirements: Readback Mode
    9. 7.9  Timing Diagrams
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  DAC Architecture
      2. 8.3.2  Voltage Output Stage
      3. 8.3.3  Current Output Stage
      4. 8.3.4  Internal Reference
      5. 8.3.5  Digital Power Supply
      6. 8.3.6  DAC Clear
      7. 8.3.7  Power-On Reset
      8. 8.3.8  Alarm Detection
      9. 8.3.9  Watchdog Timer
      10. 8.3.10 Frame Error Checking
      11. 8.3.11 User Calibration
      12. 8.3.12 Programmable Slew Rate
    4. 8.4 Device Functional Modes
      1. 8.4.1 Setting Voltage and Current Output Ranges
      2. 8.4.2 Boost Configuration for IOUT
      3. 8.4.3 Filtering the Current Output (only on the VQFN package)
      4. 8.4.4 HART Interface
        1. 8.4.4.1 For 4-mA to 20-mA Mode
        2. 8.4.4.2 For All Current Output Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Peripheral Interface (SPI)
        1. 8.5.1.1 SPI Shift Register
        2. 8.5.1.2 Write Operation
        3. 8.5.1.3 Read Operation
        4. 8.5.1.4 Stand-Alone Operation
        5. 8.5.1.5 Multiple Devices on the Bus
    6. 8.6 Register Maps
      1. 8.6.1 DACx760 Command and Register Map
        1. 8.6.1.1 DACx760 Register Descriptions
          1. 8.6.1.1.1 Control Register
          2. 8.6.1.1.2 Configuration Register
          3. 8.6.1.1.3 DAC Registers
          4. 8.6.1.1.4 Reset Register
          5. 8.6.1.1.5 Status Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Controlling the VOUT and IOUT Pins
        1. 9.1.1.1 VOUT and IOUT Pins are Independent Outputs, Never Simultaneously Enabled
        2. 9.1.1.2 VOUT and IOUT Pins are Independent Outputs, Simultaneously Enabled
        3. 9.1.1.3 VOUT and IOUT Pins are Tied Together, Never Simultaneously Enabled
      2. 9.1.2 Implementing HART in All Current Output Modes
        1. 9.1.2.1 Using CAP2 Pin on VQFN Package
        2. 9.1.2.2 Using the ISET-R Pin
      3. 9.1.3 Short-Circuit Current Limiting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information

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6 Pin Configuration and Functions

Figure 6-1 PWP (24-Pin HTSSOP) Package, Top View
Figure 6-2 RHA (40-Pin VQFN) Package, Top View
Table 6-1 Pin Functions
PIN TYPE DESCRIPTION
NAME PWP (HTSSOP) RHA (VQFN)
ALARM 3 2 Digital output Alarm pin. Open drain output. External pullup resistor required (10 kΩ). The pin goes low (active) when the ALARM condition is detected (open circuit, over temperature, timeout and so forth).
AVDD 24 36 Supply input Positive analog power supply.
AVSS 1 14, 37 Supply input Negative analog power supply in dual power-supply operation. Connects to GND in single power-supply operation.
BOOST 20 27 Analog output Boost pin. External transistor connection (optional).
CAP1 — 28 Analog input Connection for current output filtering capacitor (optional).
CAP2 — 29 Analog input Connection for current output filtering capacitor (optional).
CLR 6 5 Digital input Clear input. Logic high on this pin causes the part to enter CLEAR state. Active high.
CLR-SEL 5 4 Digital input Selects the VOUT value in CLEAR state, after power-on and reset.
CMP 17 24 Analog output External compensation capacitor connection pin (optional). Addition of the external capacitor (connected between VOUT and this pin) improves the stability with high capacitive loads at the VOUT pin by reducing the bandwidth of the output amplifier, thus increasing the settling time. If an external compensation capacitor greater than 470 pF is used, connect an additional 100-pF capacitor from CMP to GND.
DIN 9 8 Digital input Serial data input. Data are clocked into the 24-bit input shift register on the rising edge of the serial clock input. Schmitt-Trigger logic input.
DVDD 2 39 Supply input or output Digital power supply. Can be input or output, depending on DVDD-EN pin.
DVDD-EN 16 23 Digital input Internal power-supply enable pin. Connect this pin to GND to disable the internal supply, or leave this pin unconnected to enable the internal supply. When this pin is connected to GND, an external supply must be connected to the DVDD pin.
GND 4 3, Supply input Ground reference point for all digital circuitry of the device. Connect to 0 V.
GND 11, 12 12, 13, 15 Supply input Ground reference point for all analog circuitry of the device. Connect to 0 V.
HART-IN 18 25 Analog input Input pin for HART modulation.
IOUT 19 26 Analog output Current output pin
ISET-R 13 16 Analog input Connection pin for external precision resistor (15 kΩ); see Section 8.
LATCH 7 6 Digital input Load DAC registers input. A rising edge on this pin loads the input shift register data into the DAC data and control registers and updates the DAC outputs.
NC — 1, 10, 11, 19, 20, 21, 22, 30, 31, 35, 38, 40 — No connection.
REFOUT 14 17 Analog output Internal reference output. Connect to REFIN when using internal reference.
REFIN 15 18 Analog input Reference input
SCLK 8 7 Digital input Serial clock input of serial peripheral interface (SPI). Data can be transferred at rates up to 30 MHz. Schmitt-Trigger logic input.
SDO 10 9 Digital output Serial data output. Data are valid on the rising edge of SCLK.
Thermal Pad — — Supply input The thermal pad is internally connected to the AVSS supply. For enhanced thermal performance, thermally connect the pad to a copper plane. The pad can be electrically connected to the same potential as the AVSS pin (either negative supply voltage or GND) or left electrically unconnected provided a supply connection is made at the AVSS pin. The AVSS pin must always be connected to either the negative supply voltage or GND, independent of the thermal pad connection.
VOUT 21 32 Analog output Voltage output pin. This is a buffered analog voltage output.
+VSENSE 22 33 Analog input Sense pin for the positive voltage output load connection.
–VSENSE 23 34 Analog input Sense pin for the negative voltage output load connection.
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