The first method of implementing HART is to couple the signal through the CAP2 pin, as conceptualized in Figure 9-3. Note that this pin is only available in the 40-pin VQFN package.

Figure 9-3 Implementing HART on IOUT Using the CAP2 Pin

In Figure 9-3, R₃ is nominally 40 Ω, and R₂ is dependent on the current output range (set by the RANGE bits) as described below:

• 4-mA to 20-mA range: R₂ = 2.4 kΩ typical
• 0-mA to 20-mA range: R₂ = 3 kΩ typical
• 0-mA to 24-mA range: R₂ = 3.6 kΩ typical

The purpose of the 12.5-kΩ resistor is to create a filter when CAP1 and CAP2 are used.

To insert the external HART signal on the CAP2 pin, an external ac-coupling capacitor is typically connected to CAP2. The high-pass filter 3-dB frequency would be determined by the resistive impedance looking into CAP2 (R₂ + 12.5 kΩ) and the coupling capacitor value. The 3-dB frequency would be 1 /(2 × π × [R₂ + 12.5 kΩ] × [Coupling Cap Value]).

After the input HART frequency is greater than the 3-dB frequency, the ac signal is seen at the plus input of amplifier A2 and would therefore be seen across the 40-Ω resistor. To generate a 1-mA signal on the output would therefore require a 40-mV peak-to-peak signal on CAP2. Because most HART modems do not output a 40-mV signal, a capacitive divider is used in the above circuit to attenuate the FSK signal from the modem. In the above circuit, the high-pass cutoff frequency would be 1 / (2 × π × [R₂+12.5 kΩ] × [C₁ + C₂]). There is one disadvantage of this approach: if the AVDD supply was not clean, any ripple on it could couple into the part.