ZHCSHU4E April   2005  – March 2018 DAC7811

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      框图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics: VDD = 5 V
    7. 6.7 Typical Characteristics: VDD = 2.7 V
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Interface
      2. 7.4.2 Input Shift Register
      3. 7.4.3 SYNC Interrupt (Stand-Alone Mode)
      4. 7.4.4 Daisy-Chain
      5. 7.4.5 Control Bits C3 to C0
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Unipolar Operation Using DAC7811
      2. 8.1.2 Bipolar Operation Using the DAC7811
      3. 8.1.3 Stability Circuit
      4. 8.1.4 Amplifier Selection
      5. 8.1.5 Programmable Current Source Circuit
    2. 8.2 Typical Application
      1. 8.2.1 Single Supply Unipolar Multiplying DAC
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

VDD = 2.7 V to 5.5 V; IOUT1 = Virtual GND; IOUT2 = 0V; VREF = 10 V; TA = full operating temperature. All specifications –40°C to 125°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution 12 Bits
Relative accuracy ±1 LSB
Differential nonlinearity ±1 LSB
Output leakage current Data = 0000h, TA = 25°C ±5 nA
Output leakage current Data = 0000h, TA = TMAX ±25 nA
Full-scale gain error All ones loaded to DAC register ±5 ±10 mV
Full-scale tempco(1) ±5 ppm/°C
Output capacitance(1) Code dependent 5 pF
REFERENCE INPUT
Input resistance 8 10 12 kΩ
RFB resistance 8 10 12 kΩ
LOGIC INPUTS AND OUTPUT(1)
IIL Input leakage current 10 µA
CIL Input capacitance 10 pF
INTERFACE TIMING (see Figure 27)
fCLK 50 MHz
tC Clock period 20 ns
tCH Clock pulse width high 8 ns
tCC Clock pulse width low 8 ns
tCSS SYNC falling edge to SCLK active edge setup time 13 ns
tCST SCLK active edge to SYNC rising edge hold time 5 ns
tDS Data setup time 5 ns
tDH Data hold time 3 ns
tSH SYNC high time 30 ns
tDDS SYNC inactive edge to SDO valid VDD = 2.7 V 25 35 ns
VDD = 5 V 20 30 ns
POWER REQUIREMENTS
IDD (normal operation) Logic inputs = 0 V 5 µA
VDD = 4.5 V to 5.5 V VIH = VDD and VIL = GND 0.8 5 µA
VDD = 2.7 V to 3.6 V VIH = VDD and VIL = GND 0.4 2.5 µA
AC CHARACTERISTICS(1)
Output voltage settling time 0.2 µs
Reference multiplying BW VREF = 7 VPP, Data = FFFh 10 MHz
DAC glitch impulse VREF = 0 V to 10 V,
Data = 7FFh to 800h to 7FFh		 5 nV-s
Feedthrough error VOUT/VREF Data = 000h, VREF = 100 kHz –60 dB
Digital feedthrough 2 nV-s
Total harmonic distortion –105 dB
Output spot noise voltage 18 nV/√Hz
(1) Specified by design and characterization; not production tested.
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