ZHCSHU4E April 2005 – March 2018 DAC7811
PRODUCTION DATA.
Control Bits C3 to C0 allow control of various functions of the DAC; see Table 3. Default settings of the DAC on powering up are as follows: Data clocked into shift register on falling clock edges; daisy-chain mode is enabled. The device powers on with zero-scale loaded into the DAC register and IOUT lines. The DAC control bits allow the user to adjust certain features as part of an initialization sequence; for example, daisy-chaining may be disabled if not in use, active clock edge may be changed to rising edge, and DAC output may be cleared to either zero or midscale. The user may also initiate a readback of the DAC register contents for verification purposes.
| C3 | C2 | C1 | C0 | FUNCTION IMPLEMENTED |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | No operation (power-on default) |
| 0 | 0 | 0 | 1 | Load and update |
| 0 | 0 | 1 | 0 | Initiate readback |
| 0 | 0 | 1 | 1 | Reserved |
| 0 | 1 | 0 | 0 | Reserved |
| 0 | 1 | 0 | 1 | Reserved |
| 0 | 1 | 1 | 0 | Reserved |
| 0 | 1 | 1 | 1 | Reserved |
| 1 | 0 | 0 | 0 | Reserved |
| 1 | 0 | 0 | 1 | Daisy-chain disable |
| 1 | 0 | 1 | 0 | Clock data to shift register on rising edge |
| 1 | 0 | 1 | 1 | Clear DAC output to zero |
| 1 | 1 | 0 | 0 | Clear DAC output to midscale |
| 1 | 1 | 0 | 1 | Reserved |
| 1 | 1 | 1 | 0 | Reserved |
| 1 | 1 | 1 | 1 | Reserved |