8.5.1.2.2 DACx0502 I²C Update Sequence

For a single update, the DACx0502 requires a start condition, a valid I²C address byte, a command byte, and two data bytes (the most significant data byte, MSDB, and least significant data byte, LSDB), as listed in Table 2.

After each byte is received, the DACx0502 acknowledges the byte by pulling the SDA line low during the high period of a single clock pulse, as shown in Figure 62. These four bytes and acknowledge cycles make up the 36 clock cycles required for a single update to occur. A valid I²C™ address byte selects the DACx0502 devices.

Figure 62. I²C Bus Protocol

The command byte sets the operating mode of the selected DACx0502 device. When the operating mode is selected by this byte, the DACx0502 series must receive two data bytes, the most significant data byte (MSDB) and least significant data byte (LSDB), for a data update to occur. The DACx0502 devices perform an update on the falling edge of the acknowledge signal that follows the LSDB.

When using fast mode (clock = 400 kHz), the maximum DAC update rate is limited to 22.22 kSPS. Using the fast-mode plus (clock = 1 MHz), the maximum DAC update rate is limited to 55.55 kSPS. When a stop condition is received, the DACx0502 family releases the I²C bus and awaits a new start condition.