ZHCSQ74A September 2022 – November 2022 DAC82001
PRODUCTION DATA
The DAC82001 is controlled through a 3-wire serial peripheral interface (SPI) using SYNC, SCLK, and SDIN. The serial interface operates at up to 50 MHz. The input shift register is 24-bits wide.
Table 7-1 shows the SPI frame format.
| BIT | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DESC | W | Register Address - Command Byte | 16-Bit MSB-Aligned DAC Data | |||||||||||||||||||||
Serial clock SCLK is a continuous or a gated clock. The first falling edge of SYNC starts the operation cycle. When SYNC is high, the SCLK and SDIN signals are blocked. The device internal registers are updated from the shift register on the rising edge of SYNC.