A precision analog component requires careful layout. The following list provides some insight into good layout practices.

• Bypass the VDD to ground with a low ESR ceramic bypass capacitor. The typical recommended bypass capacitance is 0.1-µF to 0.22-µF ceramic capacitor, with a X7R or NP0 dielectric.
• Bypass VREF to ground with low ESR ceramic bypass capacitors.
• Place power supplies and REF bypass capacitors close to the pins to minimize inductance and optimize performance.
• The output pin, VOUT, has relatively high impedance and is susceptible to high parasitic capacitance. Use short and direct traces when routing VOUT.