For SPI operation, the SYNC line stays low for at least 24 falling edges of SCLK, and the addressed DAC register updates on the SYNC rising edge. However, if the SYNC line is brought high before the 24th SCLK falling edge, this event acts as an interrupt to the write sequence. The shift register resets and the write sequence is discarded. As Figure 7-3 shows, the data buffer contents and the DAC register contents do not update, and the operating mode does not change.