ZHCSQ41A August   2022  – December 2022 DAC82002

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagram
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Digital-to-Analog Converter (DAC) Architecture
        1. 7.3.1.1 DAC Transfer Function
        2. 7.3.1.2 DAC Register Structure
      2. 7.3.2 Power-On Reset (POR)
      3. 7.3.3 Hardware Reset
      4. 7.3.4 Software Reset
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Serial Peripheral Interface (SPI)
        1. 7.5.1.1 SYNC Interrupt
    6. 7.6 Register Maps
      1. 7.6.1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Arbitrary Waveform Generator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Bipolar Analog Output Configuration
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 术语表
  10. 10Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

6.8 Typical Characteristics

at TA = 25°C, channel A shown, and DAC outputs unloaded (unless otherwise noted)

VDD = 5.5 V, VREF = 5.0 V
Figure 6-2 Integral Linearity Error vs Digital Input Code
VDD = 5.5 V, VREF = 5.0 V
Figure 6-4 Integral Linearity Error Histogram
VDD = 5.5 V, VREF = 5.0 V
Figure 6-6 Differential Linearity Error vs Digital Input Code
VDD = 5.5 V, VREF = 5.0 V
Figure 6-8 Total Unadjusted Error vs Digital Input Code
 
Figure 6-10 Zero-Code Error vs Temperature
 
Figure 6-12 Supply Current vs Temperature
VDD = 5.5 V, VREF = 5.0 V,
DAC code transition from midscale – 1 to midscale LSB
Figure 6-14 Glitch Impulse, Rising Edge, 1-LSB Step
VDD = 2.7 V, VREF = 2.5 V
Figure 6-16 Full-Scale Settling Time, Rising Edge
VDD = 5.5 V, VREF = 5.0 V
Figure 6-18 Power-On Glitch
VDD = 5.5 V, DAC code at midscale
Figure 6-20 Power-Supply Rejection Ratio (PSRR)
 
Figure 6-22 Reference Current vs Digital Input Code
VDD = 2.7 V, VREF = 2.5 V
Figure 6-24 Control Feedthrough
VDD = 5.5V, VREF = 5.0V 
Figure 6-26 Channel-to-Channel Crosstalk
VDD = 2.7 V, VREF = 2.5 V
Figure 6-3 Integrated Linearity Error vs Digital Input Code
VDD = 2.7 V, VREF = 2.5 V
Figure 6-5 Integrated Linearity Error Histogram
VDD = 2.7 V, VREF = 2.5 V
Figure 6-7 Differential Linearity Error vs Digital Input Code
VDD = 2.7 V, VREF = 2.5 V
Figure 6-9 Total Unadjusted Error vs Digital Input Code
 
Figure 6-11 Gain Error vs Temperature
 
Figure 6-13 Power-down Current vs Temperature
VDD = 5.5 V, VREF = 5.0 V,
DAC code transition from midscale to midscale - 1 LSB
Figure 6-15 Glitch Impulse, Falling Edge, 1-LSB Step
VDD = 2.7 V, VREF = 2.5 V
Figure 6-17 Full-Scale Settling Time, Falling Edge
VDD = 5.5 V, VREF = 5.0 V
Figure 6-19 Power-Off Glitch
GUID-20220914-SS0I-HFMM-DKZ9-53LRVB0V0FQ5-low.png
VDD = 5.5 V, VREF = 5.0 V
Figure 6-21 Output Noise Density vs Frequency
VDD = 2.7 V, VREF = 2.5 V
Figure 6-23 Clock Feedthrough
 
VDD = 5.5 V, VREF = 5.0 V
Figure 6-25 RESET Response
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