ZHCSQ41A August 2022 – December 2022 DAC82002
PRODUCTION DATA
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| AGND | 4 | Ground | Ground reference point for all circuitry on the device. |
| RESET | 5 | Input | Asynchronous reset. Active low. If RESET is low, all DAC channels reset either to zero-scale (RSTSEL = AGND) or to midscale (RSTSEL = VDD). |
| RSTSEL | 3 | Input | Reset select pin. DACs power up to zero scale if RSTSEL = AGND. DACs power up to midscale if RSTSEL = VDD. |
| SCLK | 6 | Input | Serial interface clock of SPI. |
| SDIN | 8 | Input | Serial interface data input of SPI. Data are clocked into the input shift register on each falling edge of the SCLK pin. |
| SYNC | 7 | Input | Serial data enable of SPI. Active low. This input is the frame-synchronization signal for the serial data. When the signal goes low, the serial interface input shift register is enabled. |
| VDD | 1 | Power | Analog supply voltage (2.7 V to 5.5 V) |
| VOUTA | 2 | Output | Analog output voltage from DAC A |
| VOUTB | 9 | Output | Analog output voltage from DAC B |
| VREF | 10 | Input | This pin is the external reference input to the device. |