The DAC82002 device includes a power-on reset function that controls the output voltage at power up. After the V_DD supply has been established, a POR event is issued. The POR causes all registers to initialize to default values, and communication with the device is valid only after a 250-µs, power-on-reset delay. The default value for all DACs is zero code if RSTSEL = AGND, and midscale code if RSTSEL = V_DD. Each DAC channel remains at the power-up voltage until a valid command is written to a channel.

When the device powers up, a POR circuit sets the device to the default mode. Figure 7-2 shows that the POR circuit requires specific V_DD levels to make sure that the internal capacitors discharge and reset the device at power up. To make sure that a POR occurs, V_DD must be less than 0.7 V for at least 1 ms. When V_DD drops to less than 2.2 V but remains greater than 0.7 V (shown as the undefined region in Figure 7-2), the device may or may not reset under all specified temperature and power-supply conditions; in this case, initiate a POR. When V_DD remains greater than 2.2 V, a POR does not occur.

Figure 7-2 Threshold Levels for the V_DD POR Circuit