The DAC output is asynchronously set to zero code if RSTSEL = AGND, and midscale code if RSTSEL = V_DD, immediately after the RESET pin is brought low. The RESET signal resets all internal registers, meaning all registers initialize to default values. Bring the RESET pin back to high before a write sequence starts. Similar to the POR delay, communication with the device is valid only after a 250‑µs delay. The default value for each DAC channel remains at the reset voltage until a valid command is written to a channel. The RSTSEL pin can be reconfigured without a power cycle. The DAC output always reflects the current RSTSEL status when the RESET pin is pulled low.