ZHCSBK1C December 2006 – January 2018 DAC8560
PRODUCTION DATA.
The DAC8560 internal reference is enabled by default; however, the reference can be disabled for debugging or evaluation purposes. A serial command requiring at least two additional SCLK cycles at the end of the 24-bit write sequence (see Serial Interface) must be used to disable the internal reference. For proper operation, a total of at least 26 SCLK cycles are required for each enable/disable internal reference update sequence, during which SYNC must be held low. To disable the internal reference, execute the write sequence illustrated in Table 1 followed by at least two additional SCLK falling edges while SYNC is low.
To then enable the reference, either perform a power-cycle to reset the device, or sequentially execute the two write sequences in Table 2 and Table 3. Each of these write sequences must be followed by at least two additional SCLK falling edges while SYNC remains low.
During the time that the internal reference is disabled, the DAC will function normally using an external reference. At this point, the internal reference is disconnected from the VREF pin (tri-state). Do not attempt to drive the VREF pin externally and internally at the same time indefinitely.