7.5.1 Serial Interface

The DAC8560 has a 3-wire serial interface ( SYNC, SCLK, and D_IN) that is compatible with SPI, QSPI, and Microwire interface standards, as well as most DSPs. See Figure 1 for an example of a typical write sequence.

The write sequence begins by bringing the SYNC line LOW. Data from the D_IN line is clocked into the 24-bit shift register on each falling edge of SCLK. The serial clock frequency can be as high as 30 MHz, making the DAC8560 compatible with high-speed DSPs. On the 24th falling edge of the serial clock, the last data bit is clocked in and the programmed function is executed.

At this point, the SYNC line may be kept LOW or brought HIGH. In either case, it must be brought HIGH for a minimum of 33 ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. As previously mentioned, it must be brought HIGH again before the next write sequence.