8.2.2.1.1 Passive Component Selection

The amplifier in this circuit uses negative feedback to ensure that the voltages at the inverting and non-inverting terminals are equal. When the DAC output is at zero scale (0 V) the inverting terminal is a virtual ground so no current flows across R_G1; this causes the circuit to function as an inverting amplifier with gain equal to R_FB / R_G2. When the DAC output is full-scale (V_REF) the inverting terminal potential is equal to V_REF so no current flows across R_G2; this causes the circuit to function as a non-inverting amplifier with gain equal to (1 + R_FB / R_G1). A simple three-step process can be used to select the resistor values used to realize any bipolar output range using DAC8560. The internal V_REF value is 2.5 V. The desired output range for this design is ±10 V. First, using the transfer function shown in Equation 6, consider the negative full-scale output case when V_DAC is equal to 0 V, V_REF is equal to 2.5 V, and V_OUT is equal to –10 V. This case is used to calculate the ratio of R_FB to R_G2 and is shown explicitly in Equation 7.

Equation 7.

Second, consider the positive full-scale output case when V_DAC is equal to 2.5 V, V_REF is equal to 2.5 V, and V_OUT is equal to 10 V. This case is used to calculate the ratio of R_FB to R_G1 and is shown explicitly in Equation 8.

Equation 8.

Finally, seed the ideal value of R_G2 to calculate the ideal values of R_FB and R_G2. The key considerations for seeding the value of R_G2 should be the drive strength of the reference source as well as choosing small resistor values to minimize noise contributed by the resistor network. For this design R_G2 of 8.25 kΩ was chosen, which limits the peak current drawn from the reference source to approximately 333 µA under nominal conditions, well within the 20-mA limit of the DAC8560. In this case the nearest, 0.1% tolerance, 0603 package values for each resistor are ideal.

Standard values for 0.1% resistors can be an obstacle for this design and it may take multiple iterations of seeding the values to find real components or they may not exist. Workarounds can include utilizing multiple resistors in series and/or parallel, using potentiometers for analog trim calibration, or providing extra gain in the output circuit and applying digital calibration. In systems where the output voltage must reach the design-goal end-points (±10 V) it may be desirable to apply additional gain to the circuit. This approach may contribute additional overall system error since the end-point errors vary from system to system. For this design, use the exact values calculated in the design process to keep error analysis easy to follow.

To deliver a near-universal cable drive solution, choose C_LOAD to be relatively large compared to typical cable capacitance such that its capacitance dominates the reactive load seen by the output amplifier. To drive larger capacitive loads R_ISO, C_COMP, and C_LOAD may need to be adjusted. An R_ISO of 70 Ω and C_COMP of 150 pF are used for this design.

Resistor matching for the op amp resistor network is critical for the success of this design; choose components with tight tolerances. For this design 0.1% resistor values are implemented but this constraint may be adjusted based on application specific design goals. Resistor matching contributes to both offset error and gain error in this design. The tolerance of stability components R_ISO and C_COMP is not critical and 1% components are acceptable.