ZHCSBK1C December 2006 – January 2018 DAC8560
PRODUCTION DATA.
Figure 75 shows a serial interface between the DAC8560 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC8560, while the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7), similar to the 8051 diagram.
Configure the 68HC11 so that its CPOL bit is 0, and its CPHA bit is 1. This configuration causes data appearing on the MOSI output to be valid on the falling edge of SCK. When data is being transmitted to the DAC, the SYNC line is held LOW (PC7). Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. (Data is transmitted MSB first.) In order to load data to the DAC8560, PC7 is left LOW after the first eight bits are transferred, then a second and third serial write operation is performed to the DAC. PC7 is taken HIGH at the end of this procedure.