ZHCSH77D June 2017 – May 2019 DAC8740H , DAC8741H
PRODUCTION DATA.
In SPI mode, HART data is loaded into a transmit FIFO via the SPI serial interface. In UART mode, the UART baud rate matches the HART baud rate, and therefore the FIFO is bypassed. In both cases, the input data are translated into the mark and space frequency shift keyed (FSK) analog signals (1200 Hz and 2200 Hz, respectively) used in HART communication using an internal HART modulator.
The HART modulator implements a look-up table containing 32 6-bit signed values that represent a single phase continuous sinusoidal cycle. A counter is implemented that incrementally loads the table values to a digital-to-analog converter (DAC), at a clock frequency determined by the binary value of the input data, in order to create the mark and space analog output signals used to represent HART data.
The modem operates in half-duplex mode, unless placed in full-duplex mode, where the modulator and demodulator are not active simultaneously. The modem arbitrates over which component is active. To request that the modulator is activated UART devices toggle the RTS pin low, SPI devices toggle the RTS bit in the MODEM CONTROL register. These mechanics are explained in more detail in the respective sections of Device Functional Modes.
In HART mode the MOD_OUT pin requires parallel capacitance of 5 nF to 22 nF, or 0 pF to 100 pF in FOUNDATION Fieldbus and PROFIBUS PA mode for stability.