ZHCSJ40 December   2018 DAC8742H

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  HART Modulator
      2. 7.3.2  HART Demodulator
      3. 7.3.3  FOUNDATION FIELDBUS / PROFIBUS PA Manchester Encoder
      4. 7.3.4  FOUNDATION FIELDBUS / PROFIBUS PA Manchester Decoder
      5. 7.3.5  Internal Reference
      6. 7.3.6  Clock Configuration
      7. 7.3.7  Reset and Power-Down
      8. 7.3.8  Full-Duplex Mode
      9. 7.3.9  I/O Selection
      10. 7.3.10 Jabber Inhibitor
    4. 7.4 Device Functional Modes
      1. 7.4.1 UART Interfaced HART
      2. 7.4.2 UART Interfaced FOUNDATION FIELDBUS / PROFIBUS PA
      3. 7.4.3 SPI Interfaced HART
      4. 7.4.4 SPI Interfaced FOUNDATION FIELDBUS / PROFIBUS PA
      5. 7.4.5 Interface
        1. 7.4.5.1 UART
          1. 7.4.5.1.1 UART Carrier Detect
        2. 7.4.5.2 SPI
          1. 7.4.5.2.1 SPI Cyclic Redundancy Check
          2. 7.4.5.2.2 SPI Interrupt Request
    5. 7.5 Register Maps
      1. 7.5.1 CONTROL Register (Offset = 2h) [reset = 0x8042]
        1. Table 4. CONTROL Register Field Descriptions
      2. 7.5.2 RESET Register (Offset = 7h) [reset = 0x0000]
        1. Table 5. RESET Register Field Descriptions
      3. 7.5.3 MODEM_STATUS Register (Offset = 20h) [reset = 0x0000]
        1. Table 6. MODEM_STATUS Register Field Descriptions
      4. 7.5.4 MODEM_IRQ_MASK Register (Offset = 21h) [reset = 0x0024]
        1. Table 7. MODEM_IRQ_MASK Register Field Descriptions
      5. 7.5.5 MODEM_CONTROL Register (Offset = 22h) [reset = 0x0048]
        1. Table 8. MODEM_CONTROL Register Field Descriptions
      6. 7.5.6 FIFO_D2M Register (Offset = 23h) [reset = 0x0200]
        1. Table 9. FIFO_D2M Register Field Descriptions
      7. 7.5.7 FIFO_M2D Register (Offset = 24h) [reset = 0x0200]
        1. Table 10. FIFO_M2D Register Field Descriptions
      8. 7.5.8 FIFO_LEVEL_SET Register (Offset = 25h) [reset = 0x0000]
        1. Table 11. FIFO_LEVEL_SET Register Field Descriptions
      9. 7.5.9 PAFF_JABBER Register (Offset = 27h) [reset = 0x0000]
        1. Table 12. PAFF_JABBER Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Design Recommendations
      2. 8.1.2 Selecting the Crystal/Resonator
      3. 8.1.3 Included Functions and Filter Selection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 DAC8742H HART Modem
        2. 8.2.2.2 2-Wire Current Loop
        3. 8.2.2.3 Regulator
        4. 8.2.2.4 DAC
        5. 8.2.2.5 Amplifiers
        6. 8.2.2.6 Diodes
        7. 8.2.2.7 Passives
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6.5 Electrical Characteristics

All specifications over -40°C to +125°C ambient operating temperature, 2.7V ≤ AVDD ≤ 5.5V, 1.71V ≤ IOVDD ≤ 5.5V, Internal Reference, Internal Filter, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER REQUIREMENTS
IOVDD 1.71 5.5 V
AVDD 2.7 5.5 V
AVDD and IOVDD Supply Current (HART Mode)
Demodulator active External Clock, -40°C to 85°C 110 150 µA
External Clock, -55°C to 125°C 220 µA
External Clock, -40°C to 85°C, External Reference 100 140 µA
External Clock, -55°C to 125°C, External Reference 210 µA
Modulator active External Clock, -40°C to 85°C 160 180 µA
External Clock, -55°C to 125°C 250 µA
External Clock, -40°C to 85°C, External Reference 150 170 µA
External Clock, -55°C to 125°C, External Reference 240 µA
Crystal Oscillator External Crystal, 16pF at XTAL1 and XTAL2 40 65 µA
External Crystal, 36pF at XTAL1 and XTAL2 40 65 µA
Internal Oscillator External Reference 105 180 µA
SPI Interface Additional quiescent current required when interfacing via SPI 5 µA
AVDD and IOVDD Supply Current (FF/PA Mode)
Decoder active External Clock, -40°C to 85°C 160 220 µA
External Clock, -55°C to 125°C 330 µA
External Clock, -40°C to 85°C, External Reference 175 200 µA
External Clock, -55°C to 125°C, External Reference 320 µA
Encoder active External Clock, -40°C to 85°C 175 250 µA
External Clock, -55°C to 125°C 360 µA
External Clock, -40°C to 85°C, External Reference 165 235 µA
External Clock, -55°C to 125°C, External Reference 350 µA
Crystal Oscillator External Crystal, 16pF at XTAL1 and XTAL2 40 65 µA
External Crystal, 36pF at XTAL1 and XTAL2 40 65 µA
SPI Interface Additional quiescent current required when interfacing via SPI  5 µA
AVDD and IOVDD Supply Current (All Modes)
Power-Down Mode Internal reference disabled, -40°C to 85°C, no active clock input 30 60 µA
Internal reference disabled, -55°C to 125°C, no active clock input 182 µA
CLOCK REQUIREMENTS
EXTERNAL CLOCK (HART MODE)
External Clock Source Frequency 3.6864 MHz Clock 3.6469 3.6864 3.7232 MHz
1.2288 MHz Clock 1.2165 1.2288 1.2411 MHz
EXTERNAL CLOCK (FF/PA MODE)
External Clock Source Frequency 4 MHz Clock 3.96 4 4.04 MHz
INTERNAL OSCILLATOR
Frequency -40°C to 125°C 1.2165 1.2288 1.2411 MHz
VOLTAGE REFERENCE
INTERNAL REFERENCE VOLTAGE
Internal Reference Voltage 1.47 1.5 1.53 V
Load Regulation 1.3 V/mA
Capacitive Load Guaranteed by design 1 µF
OPTIONAL EXTERNAL REFERENCE VOLTAGE
External Reference Input Voltage 2.375 2.5 2.625 V
External Reference Input Current Demodulator 4.5 µA
Modulator 4.5 µA
Internal Oscillator 4.5 µA
Power-Down 4.5 µA
HART MODEM
MOD_IN INPUT (HART MODE)
Input Voltage Range External Reference Source, guaranteed by design. Signal applied at the input to the DC blocking capacitor. 0 1.5 Vp-p
Internal Reference Source, guaranteed by design. Signal applied at the input to the DC blocking capacitor. 0 1.5 Vp-p
Receiver Sensitivity Threshold for successful carrier detection and demodulation, assuming ideal sinusoidal input FSK signals with valid preamble using internal filter. 80 100 120 mVp-p
MOD_OUT OUTPUT (HART MODE)
Output Voltage AC-coupled (2.2µF), measured at MOD_OUT pin with 160Ω load 450 460 480 mVp-p
Mark Frequency Internal Oscillator 1200 Hz
Space Frequency Internal Oscillator 2200 Hz
Frequency Error Internal Oscillator, -40°C to 125°C -1 1 %
Phase Continuity Error Guaranteed by design 0 Degrees
Minimum Resistive Load 160Ω, AC coupled with 2.2µF, guaranteed by design 160 Ω
Transmit Impedance RTS low, measured at the MOD_OUT pin, 1mA measurement current 13 Ω
RTS high, measured at the MOD_OUT pin, ±200nA measurement current 250 kΩ
FF / PA MODEM
MOD_IN INPUT (FF/PA MODE)
Input Voltage Range External Reference Source, specified by design. Signal applied at the input to the DC blocking capacitor. 0 1 Vp-p
Internal Reference enabled, specified by design. Signal applied at the input to the DC blocking capacitor. 0 1 Vp-p
Receiver Jitter Tolerance Edge-to-edge measurement of Manchester Encoded waveforms -3.2 3.2 µs
Receiver Sensitivity Threshold for successful carrier detection and decoding, assuming ideal Manchester Encoded input trapezoidal signals with 6µs rise time, valid preamble byte(s) and start delimiter byte, using internal filter. 75 mVp-p
MOD_OUT OUTPUT (FF/PA MODE)
Output Voltage 800 mVp-p
Maximum Amplitude Difference Maximum difference in positive and negative amplitude signals -50 50 mV
Transmit Bit Rate 31.1875 31.25 31.3125 kbit/s
Transmit Jitter Measured with respect to ideal crossing of high time and low time -0.8 0.8 µs
Output Signal Distortion Measured peak to trough distortion for positive and negative amplitude voltage outputs -10 10 %
Rise and Fall Time 10% to 90% of peak to peak signal 8 µs
Slew Rate 10% to 90% of peak to peak signal 0.2 V/µs
DIGITAL REQUIREMENTS
DIGITAL INPUTS
VIH, Input High Voltage 0.7 x IOVDD V
VIL, Input Low Voltage 0.3 x IOVDD V
CLK_CFG0, Input High Voltage Guaranteed by design 0.8 x IOVDD V
CLK_CFG0, Input Mid-Scale Voltage Guaranteed by design 0.4 x IOVDD 0.55 x IOVDD V
CLK_CFG0, Input Low Voltage Guaranteed by design 0.15 x IOVDD
Input Current -1 1 µA
Input Capcitance 5 pF
DIGITAL OUTPUTS
VOH, Output High Voltage 200µA source/sink IOVDD - 0.5 V
VOL, Output Low Voltage 200µA source/sink 0.4 V
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