The DAC has an asynchronous clear function through the CLR pin that is active-high and allows the current output to be cleared to zero-scale code. When the CLR signal returns to low, the output remains at the cleared value. The preclear value can be restored by pulsing the LATCH signal without clocking any data. A new value cannot be programmed until the CLR pin returns to low. To avoid glitches on the output, disable the output by writing a 0 to the OUTEN bit of the Control Register before changing the current range.