The device implements a user-calibration function (enabled by the CALEN bit in the Configuration Register) to trim system gain and zero errors. The DAC output is calibrated according to the value of the gain calibration and zero calibration registers. The range of gain adjustment is typically ±50% of full-scale with 1 LSB per step. The gain register must be programmed to 0x8000 to achieve the default gain of 1 because the power-on value of the register is 0x0000, equivalent to a gain of 0.5. The zero code adjustment is typically ±32,768 LSBs with 1 LSB per step. The input data format of the gain register is unsigned straight binary, and the input data format of the zero register is 2's complement. The gain and offset calibration is described by Equation 4.

Equation 4.

where

• CODE is the decimal equivalent of the code loaded to the DAC data register at address 0x01
• N is the bits of resolution (16 for DAC8750 and 12 for DAC7750)
• User_ZERO is the signed 16-bit code in the zero register
• User_GAIN is the unsigned 16-bit code in the gain register
• CODE_OUT is the decimal equivalent of the code loaded to the DAC (limited between 0x0000 to 0xFFFF for DAC8750 and 0x000 to 0xFFF for DAC7750)

This is a purely digital implementation and the output is still limited by the programmed value at both ends of the current output range (set by the RANGE bits, as described in Section 8.4.1). In addition, the correction only makes sense for endpoints inside of the true device end points. To correct more than just the actual device error (for example, a system offset), the valid range for the adjustment changes accordingly and must be taken into account.

New calibration codes are only applied to subsequent writes to the DAC data register. Updating the calibration codes does not automatically update the DAC output. Additionally, before applying new DAC data, configure the calibration codes along with the slew rate control.