The first method to implement HART is to couple the signal through the CAP2 pin, as shown in Figure 9-1.

Figure 9-1 Implementing HART on IOUT Using the CAP2 Pin

In Figure 9-1, R₃ is nominally 40 Ω, and R₂ depends on the current output range (set by the RANGE bits), described as follows:

• 4-mA to 20-mA range: R₂ = 2.4 kΩ (typical)
• 0-mA to 20-mA range: R₂ = 3 kΩ (typical)
• 0-mA to 24-mA range: R₂ = 3.6 kΩ (typical)

The purpose of the 12.5-kΩ resistor is to create a filter when CAP1 and CAP2 are used.

To insert the external HART signal on the CAP2 pin, an external ac-coupling capacitor is typically connected to CAP2. The high-pass filter 3-dB frequency is determined by the resistive impedance looking into
CAP2 (R₂ + 12.5 kΩ) and the coupling-capacitor value. The 3-dB frequency is 1 / (2 × π × [R₂ + 12.5 kΩ] × [Coupling Capacitor Value]).

When the input HART frequency is greater than the 3-dB frequency, the ac signal is seen at the plus input of amplifier A2, and is therefore seen across the 40-Ω resistor. To generate a 1-mA signal on the output therefore requires a 40-mV peak-to-peak signal on CAP2. Most HART modems do not output a 40-mV signal; therefore, a capacitive divider is used in Figure 9-1 to attenuate the FSK signal from the modem. In Figure 9-1, the high-pass cutoff frequency is 1 / (2 × π × [R₂+ 12.5 kΩ] × [C₁ + C₂]). There is one disadvantage to this approach: if the AVDD supply is not clean, any ripple on the supply could couple into the device.