The slew rate control feature controls the rate at which the output voltage or current changes. With the slew rate control feature disabled, the output changes smoothly at a rate limited by the output drive circuitry and the attached load.

To reduce the slew rate, enable the slew rate control feature through bit 4 of Table 8-17. With this feature enabled, the output does not slew directly between the two values. Instead, the output steps digitally at a rate defined by bits [7:5] (SRSTEP) and bits [11:8] (SRCLK) of the control register. SRCLK defines the rate at which the digital slew updates; SRSTEP defines the amount by which the output value changes at each update. If the DAC data register is read while the DAC output is still changing, the instantaneous value is read. Table 8-5 lists the slew rate step-size options. Table 8-6 summarizes the slew rate update clock options.

The time required for the output to slew over a given range can be expressed as Equation 7:

Equation 7.

where

• Slew Time is expressed in seconds
• Output Change is expressed in amps (A) for IOUT or volts (V) for VOUT

When the slew rate control feature is enabled, all output changes happen at the programmed slew rate. This configuration results in a staircase formation at the output. If the CLR pin is asserted, the output slews to the zero-scale value at the programmed slew rate. To verify that the slew operation has completed, read Bit 1 (SR-ON) of the Status Register. The update clock frequency for any given value is the same for all output ranges. The step size, however, varies across output ranges for a given value of step size because the LSB size is different for each output range. Figure 8-5 illustrates an example of IOUT slewing at a rate set by the previously described parameters. In this example for the DAC8760 (LSB size of 305 nA for the 0-mA to 20-mA range), the settings correspond to an update clock frequency of 6.9 kHz and a step size of 128 LSB. As shown for the case with no capacitors on CAP1 or CAP2, the steps occur at the update clock frequency (6.9 kHz corresponds to a period close to 150 µs) and the size of each step is about 38 µA (128 × 305 nA). The slew time for a specific code change can be calculated using Equation 7.

Figure 8-5 IOUT vs Time With Digital Slew Rate Control

Apply the desired programmable slew rate control setting prior to updating the DAC data register because updates to the DAC data register in tandem with updates to the slew rate control registers can create race conditions that may result in unexpected DAC data.